Sr Staff R&D Engineer - Enterprise SerDes Physical Implementation

Synopsys Inc; Agrate Brianza; In loco; EUR 70.000 - 90.000; Tempo pieno

Descrizione del lavoro

A leading technology company in Agrate Brianza seeks a Sr Staff R&D Engineer to lead high-speed interface implementations. You will mentor a team and work on cutting-edge SERDES technologies, requiring 12+ years of design experience and strong scripting skills. This role offers competitive health and financial benefits.

Servizi

Comprehensive health benefits

Financial benefits

Wellness programs

Competenze

• 12+ years in digital or physical design, comfortable leading teams.
• Deep understanding of ASIC design cycle and FinFET nodes.
• Experience with mixed-signal verification and SOC integration.

Mansioni

• Lead physical implementation of high-speed interface IPs from RTL to GDSII.
• Mentor and manage a small engineering team.
• Drive advanced SERDES projects at latest process nodes.

Conoscenze

Digital design experience

Physical design experience

Project leadership

Scripting skills (Perl, Tcl, Python)

Descrizione del lavoro

Sr Staff R&D Engineer – Enterprise SerDes Physical Implementation

Join to apply for the Sr Staff R&D Engineer – Enterprise SerDes Physical Implementation role at Synopsys Inc.

At Synopsys, we drive innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence—from self‑driving cars to learning machines. Join us to transform the future through continuous innovation.

You Are

An experienced engineer with 12+ years in digital or physical design, you’re comfortable leading teams and driving project tape‑outs. You’re skilled in the full ASIC design cycle, advanced FinFET nodes, and mixed‑signal IPs. Adaptable, communicative, and methodology‑driven, you thrive in collaborative, fast‑paced environments and are ready to travel internationally as needed.

What You’ll Be Doing

• Lead physical implementation of high‑speed interface IPs from RTL to GDSII.
• Mentor and manage a small engineering team.
• Collaborate with front‑end, analog, CAD, and product teams.
• Develop timing constraints and design architectures.
• Drive advanced SERDES projects at latest process nodes.
• Automate flows using scripting and CAD methodologies.

The Impact You Will Have

• Deliver cutting‑edge mixed‑signal IP solutions.
• Enhance SERDES platform reliability and performance.
• Lead cross‑functional project teams to success.
• Advance Synopsys’ industry reputation.
• Mentor junior engineers and foster team growth.
• Contribute to breakthrough silicon technologies.

What You’ll Need

• 12+ years digital/physical design experience with project leadership.
• Deep understanding of ASIC design cycle and FinFET nodes.
• Experience with mixed‑signal verification and SOC integration.
• Strong scripting skills (Perl, Tcl, Python).
• Ability to travel internationally.

The Team You’ll Be A Part Of

Join our Mixed‑Signal IP group—experts in high‑speed SERDES and complex mixed‑signal designs, collaborating to deliver world‑class solutions.

Rewards and Benefits

We offer comprehensive health, wellness, and financial benefits. Your recruiter will provide more details about salary and benefits during the process.