Sr SOC Physical Design Engineer, Hardware Compute Group

Amazon; Asti; In loco; EUR 60.000 - 90.000; Tempo pieno

Descrizione del lavoro

A leading global technology firm is seeking a Sr. SOC Physical Design Engineer to innovate in ASIC design, focusing on power-performance-area tradeoffs and collaborating with various teams to deliver high-quality design. This position requires extensive experience in ASIC Physical Design and proficiency in CAD tools to drive design automation and methodology improvements.

Competenze

• 7+ years in ASIC Physical Design with FINFET technologies.
• Expertise in using CAD tools for physical design tasks.
• Scripting experience for design flow automation.

Mansioni

• Drive architectural feasibility studies in physical design.
• Implement block physical design through various methods.
• Collaborate with third party design services for quality.

Conoscenze

ASIC Physical Design

RTL to GDSII

CAD tools

Scripting (Tcl, Perl, Python)

Communication skills

Formazione

BS in Electrical Engineering or Computer Science

MS or PhD in Computer Engineering/Electrical Engineering

Strumenti

Cadence

Mentor Graphics

Synopsys

Descrizione del lavoro

Sr SOC Physical Design Engineer, Hardware Compute Group

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.

Work hard. Have fun. Make history.

Responsibilities

• Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level.
• Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
• Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals.
• Contribute to developing physical design methodologies.
• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams.

Basic Qualifications

• BS in EE/CS
• 7+ years in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm
• Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
• Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation

Preferred Qualifications

• MS or PhD degree in Computer Engineering/Electrical Engineering or related field
• Excellent communication and analytical skills
• Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
• 7+ years integrating IP and ability to specify and drive IP requirements in the physical domain
• Thorough knowledge of device physics, custom/semi-custom implementation techniques
• Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc.
• Experience in extraction of design parameters, QOR metrics, and analyzing trends
• Experience with DFT & DFM flows
• Ability to provide mentorship, guidance to junior engineers and be a very effective team player

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