Sr. Physical Design Engineer - Full Chip, Hardware Compute Group

Amazon; Asti; In loco; EUR 75.000 - 95.000; Tempo pieno

Descrizione del lavoro

A leading tech company in Italy is seeking a Sr. Physical Design Engineer to innovate on semiconductor designs, including Low power SOCs and physical design processes. The ideal candidate has over 10 years of experience, strong communication skills, and proficiency with front-end and back-end implementation tools. Join us to be part of a team that's shaping the future of edge computing.

Competenze

• 10+ years of practical semiconductor implementation experience required.
• Proficiency in chip front-end and back-end implementation tools is necessary.
• Experience with memory compiler is preferred.

Mansioni

• Collaborate with architecture, timing, and logic design teams.
• Perform I/O, bump & RDL planning, and hard IP integration.
• Drive physical design and timing closure including verification.

Conoscenze

Scripting experience with Perl, Python, Tcl, and shell

Communication skills

Analytical skills

Formazione

University graduate degree or higher in EE, CE, or CS

Strumenti

Fusion Compiler

Design Compiler

ICC2

Innovus

Primetime

Tempus

Descrizione del lavoro

Sr. Physical Design Engineer - Full Chip, Hardware Compute Group

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.
Work hard. Have fun. Make history.

Roles & Responsibilities

• Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs.
• Perform I/O, bump & RDL planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation.
• Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT).
• Be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.
• Be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
• Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
• Supervise and mentor other engineers.

Basic Qualifications

• University graduate degree or higher in EE, CE, or CS.
• 10+ years or more of practical semiconductor implementation experience.
• Scripting experience with Perl, Python, Tcl, shell and drive to automate flows.
• Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus.
• Must have good communication and analytical skills.
• Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

Preferred Qualifications

• MS/PhD in Computer Science, Electrical Engineering, or related field.
• Experience with memory compiler.
• Experience with formal equivalence – Cadence Conformal/Synopsys Formality.
• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification.
• Experience with DFT and DFM flows.

Inclusive Culture & Accommodations

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Equal Opportunity Statement

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.