Attiva gli avvisi di lavoro via e-mail!

Sr. Asic Design Engineer

Experteer Italy

Parma

In loco

EUR 40.000 - 60.000

Tempo pieno

12 giorni fa

Genera un CV personalizzato in pochi minuti

Ottieni un colloquio e una retribuzione più elevata. Scopri di più

Descrizione del lavoro

A technology company in Parma is looking for a Sr. ASIC Design Engineer to develop specifications and design modules for innovative Computer Vision processors. Candidates should have a Master’s degree in Electrical Engineering and experience with VLSI/ASIC design, as well as knowledge of hardware description languages. Strong communication skills and teamwork are essential for this role.

Competenze

  • 0-4 years of experience in ASIC design.
  • Very good understanding of VLSI/ASIC design.
  • Good knowledge in hardware description languages.

Mansioni

  • Develop micro-architecture specifications for Computer Vision processor.
  • Design and implement Verilog/SystemVerilog modules for SOCs.
  • Conduct design integration, logic synthesis, and optimization.

Conoscenze

VLSI/ASIC design
Computer architecture
Logic design
Verilog/SystemVerilog
Scripting languages (Python, Perl)
Design verification
Image/Video processing
Machine learning
Strong communication skills
Team player

Formazione

Master’s degree in Electrical Engineering
Descrizione del lavoro
AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

We’re growing! Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer.

Responsibilities
  • Developing micro-architecture specifications for a next generation Computer Vision processor;
  • Designing and implementing Verilog/SystemVerilog modules for cutting edge SOCs. Examples of such modules include:
    • Video compression logic
    • Image processing logic
    • Vector processors
    • Device / Memory controllers
  • Design integration, logic synthesis, and design optimization for timing, area and power;
  • Developing front-end methodologies and tool flows;
Requirements
  • Master’s degree in Electrical Engineering with 0-4 years of experience;
  • Very good understanding of VLSI/ASIC design, Computer architecture and Logic design;
  • Good knowledge and experience in using hardware description languages (Verilog/SystemVerilog);
  • Ability to program in scripting languages, like Python and Perl;
  • Knowledge of design verification, and functional coverage;
  • Strong communication skills and a good team player;
  • Knowledge of logic synthesis and timing closure is a must;
  • Knowledge and/or experience in the areas of Image/Video processing, computer vision, machine learning are plus;

To apply, please submit resume with subject: JOB#VLSI to careers-it@ambarella.com or apply online on Ambarella website.

As an Equal Opportunity/Affirmative Action Employer, Vislab and Ambarella recruit qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status.

Please find at this link our privacy disclaimer dedicated to candidates data, accordingly to the GDPR: https://tinyurl.com/yd66nbsa

Ottieni la revisione del curriculum gratis e riservata.
oppure trascina qui un file PDF, DOC, DOCX, ODT o PAGES di non oltre 5 MB.