SoC Verification Engineer - UVM & Digital IPs | Hybrid

Fondazione Chips-IT; Cascina Vignazza; Ibrido; EUR 40.000 - 70.000; Tempo pieno

Descrizione del lavoro

A nonprofit research and technology organization in Italy is seeking an experienced Verification Engineer. You will support the development and validation of advanced digital IPs and SoC platforms, focusing on creating verification environments and collaborating with design teams. The role offers competitive compensation and a hybrid work policy, making it ideal for candidates with a strong background in digital design verification and UVM methodology.

Servizi

Competitive compensation

Lunch tickets

Private health care coverage

Training opportunities

Networking opportunities

International environment

Competenze

• At least 5 years of experience in digital design verification.
• Hands-on experience with simulation and debug tools.
• Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.

Mansioni

• Define and implement verification strategies at IP and SoC levels.
• Develop and maintain UVM-based verification environments.
• Collaborate with design, architecture, and software teams.

Conoscenze

SystemVerilog

UVM methodology

Debugging tools (e.g., QuestaSim, VCS, Verdi)

Teamwork

Documentation skills

Formazione

Master's degree in Electrical Engineering or related field

Strumenti

QuestaSim

VCS

Verdi

Descrizione del lavoro

A nonprofit research and technology organization in Italy is seeking an experienced Verification Engineer. You will support the development and validation of advanced digital IPs and SoC platforms, focusing on creating verification environments and collaborating with design teams. The role offers competitive compensation and a hybrid work policy, making it ideal for candidates with a strong background in digital design verification and UVM methodology.