Senior SoC Verification Engineer — Hybrid (UVM, Formal)

Ic Resources; Lazio; Ibrido; EUR 30.000 - 50.000; Tempo pieno

Descrizione del lavoro

A leading semiconductor organization is seeking an experienced Senior Design Verification Engineer to join their team in Rome. This role offers the chance to contribute to innovative SoC designs that will shape the future of AI and HPC. The ideal candidate will have a Master's degree and proven experience in verification methodologies, with expertise in UVM and System Verilog. The position allows for a hybrid working model. For application, contact via email.

Competenze

• Proven experience in 3 successful tapeouts.
• Knowledge of NoC, PCIe, DDR and other standard peripherals is desirable.

Mansioni

• Contribute to game-changing semiconductor technology.
• Work with advanced SoC designs in a multicultural team.

Conoscenze

UVM

System Verilog

Scripting languages (Python, Perl, Bash)

Formal Verification

Formazione

Master's degree in a relevant field

Strumenti

NoC

PCIe

DDR

Descrizione del lavoro

A leading semiconductor organization is seeking an experienced Senior Design Verification Engineer to join their team in Rome. This role offers the chance to contribute to innovative SoC designs that will shape the future of AI and HPC. The ideal candidate will have a Master's degree and proven experience in verification methodologies, with expertise in UVM and System Verilog. The position allows for a hybrid working model. For application, contact via email.