Senior DV Engineer: SoC, UVM & Emulation

Amazon; Milano; In loco; EUR 70.000 - 90.000; Tempo pieno

Descrizione del lavoro

A global leader in technology is seeking a Senior Design Verification Engineer in Milano, Italy. In this role, you will enhance hardware designs and implement verification methodologies for advanced functional blocks. The ideal candidate should have over 10 years of ASIC experience and proficiency in SystemVerilog and UVM. Join a culture that empowers innovation and delivers results for customers.

Competenze

• 10+ years of practical semiconductor ASIC experience.
• Demonstrated success in test plan development and verification infrastructure.
• Experience verifying complex IP blocks integrated into SOCs.

Mansioni

• Architect and implement verification environments for complex functional blocks.
• Collaborate with design engineers, SW, and architects to develop comprehensive test plans.
• Drive complex RTL and TB debugs.

Conoscenze

SystemVerilog

UVM

Python

Perl

RTL development

Test plan development

Low power verification

Formazione

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Strumenti

ASIC tools

FPGA

Descrizione del lavoro

A global leader in technology is seeking a Senior Design Verification Engineer in Milano, Italy. In this role, you will enhance hardware designs and implement verification methodologies for advanced functional blocks. The ideal candidate should have over 10 years of ASIC experience and proficiency in SystemVerilog and UVM. Join a culture that empowers innovation and delivers results for customers.