Senior Digital ASIC Design Engineer

Ic Resources; Parma; In loco; EUR 60.000 - 80.000; Tempo pieno

Descrizione del lavoro

A semiconductor design company based in Parma is seeking a Senior Digital ASIC Design Engineer. In this role, you will engage in low-power video compression and image processing technology. The ideal candidate will have a strong background in Digital ASIC Design, proficient Verilog/SystemVerilog skills, and familiarity with the full design flow. Flexible working options are available, providing a chance to work on cutting-edge technologies.

Competenze

• Solid background in Digital ASIC Design and IP integration.
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus.
• Familiar with ASIC synthesis; FPGA implementation experience is a bonus.

Mansioni

• Work in a growing team of multi-skilled engineers across technical disciplines.
• Handle RTL design, simulation, and technical documentation.
• Understand the full digital design flow (RTL, verification, synthesis, gate-level simulation).

Conoscenze

Verilog

SystemVerilog

Digital ASIC Design

IP integration

Formazione

Degree in Computer Science, Computer Engineering, Electrical Engineering

Strumenti

ASIC synthesis

FPGA implementation

Descrizione del lavoro

Senior Digital ASIC Design Engineer - Parma

This client is looking for a Senior Digital ASIC Design Engineer to join their team.

Working for a US-based, fabless semiconductor design company, focusing on low-power, high-definition and Ultra HD video compression, image processing, and computer vision processors for AI applications.

You will be working in a growing team of multi-skilled engineers across technical disciplines such as digital / analog / mixed-signal in design, verification and physical design.

Offering flexible working and an opportunity to work on the latest technologies and methods!

• Degree in Computer Science, Computer Engineering, Electrical Engineering, or similar
• Solid background in Digital ASIC Design and IP integration
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus
• Hands-on with RTL design, simulation, and technical documentation
• Familiar with ASIC synthesis; FPGA implementation experience is a bonus
• Understanding of the full digital design flow (RTL, verification, synthesis, gate-level simulation)
• Exposure to image / video processing, computer vision, or machine learning is advantageous

Email - [e-mail]

Tel - 01189073075

LinkedIn -