Senior Digital ASIC Design Engineer

Doxee; Modena; In loco; EUR 50.000 - 70.000; Tempo pieno

Descrizione del lavoro

A semiconductor design company in Modena is in search of a Senior Digital ASIC Design Engineer to join their expanding team. You will be tasked with developing low-power, high-definition video compression technologies, collaborating with a diverse group of engineers skilled in various technical disciplines. The ideal candidate should have a deep understanding of Digital ASIC Design along with proficiency in Verilog and SystemVerilog. A full-time position offering flexible working and a chance to engage with the latest advancements in semiconductor technology awaits you.

Competenze

• Solid background in Digital ASIC Design and IP integration.
• Hands-on with RTL design, simulation, and technical documentation.
• Understanding of the full digital design flow including verification and synthesis.

Mansioni

• Join a team working on low-power, high-definition video compression.
• Work on image processing and computer vision processors for AI applications.

Conoscenze

Digital ASIC Design

Verilog

SystemVerilog

RTL design

ASIC synthesis

FPGA implementation

image processing

machine learning

Formazione

Degree in Computer Science, Computer Engineering, Electrical Engineering

Descrizione del lavoro

Principal Recruitment Consultant at IC Resources - Semiconductor Engineering division

This client is looking for a Senior Digital ASIC Design Engineer to join their team.

Working for a US-based, fabless semiconductor design company, focusing on low‑power, high‑definition and Ultra HD video compression, image processing, and computer vision processors for AI applications.

You will be working in a growing team of multi‑skilled engineers across technical disciplines such as digital/analog / mixed‑signal in design, verification and physical design.

Offering flexible working and an opportunity to work on the latest technologies and methods!

Key Qualifications

• Degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
• Solid background in Digital ASIC Design and IP integration
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus
• Hands‑on with RTL design, simulation, and technical documentation
• Familiar with ASIC synthesis; FPGA implementation experience is a bonus
• Understanding of the full digital design flow (RTL, verification, synthesis, gate‑level simulation)
• Exposure to image/video processing, computer vision, or machine learning is advantageous

Contact

Tel – 01189073075

LinkedIn – https://www.linkedin.com/in/jordan-browne-b4a08b20b/

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function / Industries

Staffing and Recruiting