Digital IC Verification Engineer

ic resources; Parma; In loco; EUR 40.000 - 60.000; Tempo pieno

Descrizione del lavoro

A leading company in power electronics based in Emilia-Romagna is seeking a UVM Verification Engineer to join their growing team. Responsibilities include developing test plans and building reusable verification models. Ideal candidates will have strong knowledge of HDL, experience in scripting languages like Tcl and Python, and familiarity with ASIC design flow. Competitive salary and opportunities for growth are offered.

Competenze

• Knowledge of HDL for creating testbenches.
• Experience in scripting languages such as Tcl and Python.
• Familiarity with ASIC design flow and verification steps.

Mansioni

• Develop test plans and verification infrastructure using UVM methodology.
• Build reusable bus functional models and verification components.
• Perform coverage-driven verification and simulations.

Conoscenze

HDL (SystemVerilog / Verilog / VHDL)

Scripting languages (Tcl, Python)

Digital RTL design

Strumenti

Questasim

Xcelium

Git

Descrizione del lavoro

Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer.

Job duties:

• Developing test plans, tests and verification infrastructure using SV / UVM methodology
• Building reusable bus functional models, monitors, checkers and scoreboards
• Performing coverage driven verification closure
• Performing block level, multi-block level and system-level verification
• Performing Gate level simulations
• Performing Mixed Signal simulationsImplementing Regression tests
• Performing Formal Verification
• Working closely with IC designers and post-silicon engineers

Qualifications and Background

Requirements:

• Knowledge / experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation
• Knowledge / experience in scripting languages, such as Tcl and Python
• Some knowledge of ASIC design flow and related verification step

Nice to have:

• Some experience in digital RTL design
• Knowledge of UVM environments and classes
• Some experience with main EDA vendors simulators such as Questasim and Xcelium
• Knowledge of DFT structures and test pattern generation
• Some experience in silicon validation / characterisation
• Experience working on Git.

For more information, please contact Rob Hudson.