Digital Ic Verification Engineer

Ic Resources; Fidenza; Ibrido; EUR 50.000 - 70.000; Tempo pieno

Descrizione del lavoro

A leading semiconductor design company in Italy is seeking a Senior Digital ASIC Design Engineer to work on innovative low-power solutions. This role involves collaborating with a team of skilled engineers on advanced digital designs and AI technologies. Candidates should have a solid ASIC design background and strong skills in Verilog/SystemVerilog. Join this dynamic team and take advantage of flexible working arrangements.

Servizi

Flexible working

Opportunity to work on latest technologies

Competenze

• Solid background in Digital ASIC Design and IP integration.
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus.
• Understanding of the full digital design flow (RTL, verification, synthesis, gate-level simulation).

Mansioni

• Work within a team of multi-skilled engineers across various disciplines.
• Focus on low-power, high-definition video compression and image processing.
• Participate in designing and verifying digital solutions for AI applications.

Conoscenze

Digital ASIC Design

Verilog

SystemVerilog

RTL design

Technical documentation

Formazione

Degree in Computer Science, Computer Engineering, Electrical Engineering or similar

Strumenti

ASIC synthesis

FPGA implementation

Descrizione del lavoro

43122 Parma, Emilia Romagna IC Resources

This client is looking for a Senior Digital ASIC Design Engineer to join their team.

Working for a US-based, fabless semiconductor design company, focusing on low-power, high-definition and Ultra HD video compression, image processing, and computer vision processors for AI applications.

You will be working in a growing team of multi-skilled engineers across technical disciplines such as digital/analog / mixed-signal in design, verification and physical design.

Offering flexible working and an opportunity to work on the latest technologies and methods!

• Degree in Computer Science, Computer Engineering, Electrical Engineering, or similar
• Solid background in Digital ASIC Design and IP integration
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus
• Hands-on with RTL design, simulation, and technical documentation
• Familiar with ASIC synthesis; FPGA implementation experience is a bonus
• Understanding of the full digital design flow (RTL, verification, synthesis, gate-level simulation)
• Exposure to image/video processing, computer vision, or machine learning is advantageous