Digital IC Design Engineer

ic resources; Bologna; In loco; EUR 30.000 - 45.000; Tempo pieno

Descrizione del lavoro

A leading company seeks a junior digital IC designer to join their team in Bologna. The role involves VHDL design, verification of digital IPs, and collaboration with R&D on next-gen ASICs. Ideal candidates should possess a relevant degree and several years of experience in the field.

Competenze

• 3-10+ years related experience in IC design.
• Strong knowledge of CMOS technology and manufacturing process.
• Experience with digital or mixed-signal verification.

Mansioni

• Design and verify core functional blocks using VHDL, Verilog, or System-Verilog.
• Conduct silicon validation activities with lab instrumentation.
• Collaborate with R&D for the development of new IPs.

Conoscenze

CMOS technology

VHDL

Verilog

System-Verilog

Programming languages

ASIC design flow

EDA tools

English (written and spoken)

Formazione

PhD in Microelectronics

MS Degree in Physics

Strumenti

Cadence

Synopsys Design Framework

Descrizione del lavoro

To strengthen their existing IC design team, my client are currently looking for a junior digital IC designer. The engineer requested for this position will be responsible for design, simulation and full validation of several programmable functional units within a complex IC device, which is at the core of their flagship power adapter product. you will be reporting to the head of the IC team. The selected person will work in close collaboration with our R&D team for the development of new IPs to be integrated into the next generation ASICs.

Main Responsibilities :

You should be a motivated and proactive engineer, able to work well within an independent team and ready to be involved in :

• VHDL / Verilog / System-Verilog design at RT-Level of core functional blocks
• Implementation of RTL-to-Syn IC design flow, including timing / power analysis
• Verification of digital IPs using simulation tools at different abstraction level (from RTL to post-layout)
• Co-simulation of digital and analog IPs to validate the whole mixed-signal system
• FPGA prototyping of core digital IPs
• Silicon validation activities with laboratory instrumentation

Qualifications and Background

• PhD or MS Degree in Microelectronics or Physics
• 3-10+ years related experience
• Strong knowledge of the CMOS technology, standard logic libraries and manufacturing process
• Good knowledge of VHDL or Verilog or System-Verilog language
• Basic knowledge of programming and scripting languages like C++, TCL, bash, Perl
• Good experience of translating design requirements into RTL description
• Experience of digital or mixed-signal verification activities, testbench and verification planning, regression tests
• Consolidated knowledge on complete ASIC design flow (from RTL to GDSII)
• Good knowledge of existing EDA tools (Cadence or Synopsys Design Framework)
• Good English knowledge (written and spoken)

Nice to have

• Basic knowledge of some modelling languages like Verilog-A or VHDL-AMS
• Good knowledge of microprocessor design (architecture, definition of a custom ISA, implementation data / memory bus)

Design Engineer • Bologna, Emilia Romagna