CPU Microarchitecture & RTL Design Engineer (Low Power)

Qualcomm; Roma; On-site; EUR 54,000 - 80,000; Full time

Job summary

Qualcomm Europe, Inc. Italy Branch Office is seeking an Engineer for CPU RTL development targeting high performance, low power devices. You will collaborate with chip architects to conceive micro-architecture and help define architecture through early product life-cycle involvement.

You will perform performance exploration with the CPU modeling team, own RTL development and verification, and work with cross-functional teams to ensure timing, area and reliability targets are met.

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Performance exploration with CPU modeling team.
• Microarchitecture development and specification from high-level exploration to detailed spec.
• RTL ownership and refinement to meet power, performance, area and timing goals.
• Functional verification support for the verification team.
• Performance verification support to ensure RTL meets performance goals.
• Design delivery with multi-functional engineering teams for timing, area and reliability.

Skills

Microprocessor architecture

Fetch/Decode

Branch prediction

Out-of-order execution

Register renaming

Low power techniques

Verilog

VHDL

Simulators

Python/Perl scripting

Education

Bachelor's degree

Master's degree

PhD

Tools

Verilog

VHDL

Simulation tools

Job description

Qualcomm Europe, Inc. Italy Branch Office is seeking an Engineer for CPU RTL development targeting high performance, low power devices. You will collaborate with chip architects to conceive micro-architecture and help define architecture through early product life-cycle involvement.

You will perform performance exploration with the CPU modeling team, own RTL development and verification, and work with cross-functional teams to ensure timing, area and reliability targets are met.