Static Timing Analysis (STA) Engineer | Logicsemi Technologies | Bangalore / Hyderabad

Logicsemi Technologies Pvt Ltd.; Bengaluru, Hyderabad; On-site; INR 2,600,000 - 3,400,000; Full time

Job summary

Logicsemi Technologies Pvt Ltd. in Bangalore or Hyderabad seeks a Static Timing Analysis (STA) Engineer to own timing closure and signoff across advanced ASIC/SoC designs. 4+ years in VLSI STA and hands-on PrimeTime are required, with strong SDC constraint development.

You will collaborate with cross-functional teams to analyze setup/hold timing, MMMC reports, and ECO implementation, ensuring robust timing convergence and on-time tape-out. Immediate to 30 days notice preferred.

Qualifications

• Bachelors or Masters in Electronics Engineering, VLSI Design, Electrical Engg, or related field.
• 4+ years of experience in semiconductor engineering, ASIC design, and STA.
• Hands-on PrimeTime timing analysis and signoff experience.
• In-depth knowledge of SDC timing constraints development and validation.
• MMM C analysis, false paths, multicycle paths, and generated clocks.

Responsibilities

• Execute STA and timing signoff for complex ASIC/SoC designs.
• Develop, validate, and optimize SDC timing constraints for high-speed digital ICs.
• Analyze MMMC signoff reports and clock domain crossing considerations.
• Collaborate with PD teams for ECO implementation and timing convergence.
• Maintain timing reports, constraint documentation, and signoff audit logs.

Skills

Synopsys PrimeTime

SDC Timing Constraints

MMMC Analysis

Timing Closure

ECO Implementation

Scripting (Tcl/Python)

Education

Bachelor’s or Master’s in Electronics/VLSI Design

Tools

Jira

Confluence

Job description

Position Summary

Driving advanced semiconductor design closure, static timing analysis (STA), and signoff excellence across complex ASIC and SoC architectures, Logicsemi Technologies is actively seeking a skilled Static Timing Analysis (STA) Engineer for a permanent engineering engagement in Bangalore or Hyderabad. In this vital semiconductor engineering role, you will architect, execute, and validate timing closure flows, constraint development, and signoff analyses utilizing industry-standard EDA tools. Bringing 4+ years of progressive professional experience in VLSI design and STA, you will empower semiconductor development teams to achieve uncompromised silicon performance and first-pass tape-out success. This prestigious career opportunity offers competitive remuneration, high technical visibility, and exceptional professional growth within a premier semiconductor engineering enterprise.

Detailed Job Description

As a Static Timing Analysis (STA) Engineer supporting Logicsemi Technologies in Bangalore or Hyderabad, India, you will take full operational, tactical, and technical ownership of static timing analysis, signoff verification, constraint validation, and timing closure support across advanced ASIC and SoC designs. Your day-to-day responsibilities include performing setup and hold timing analysis using Synopsys PrimeTime, developing and validating SDC timing constraints, analyzing multi-mode multi-corner (MMMC) signoff reports, and collaborating with physical design teams on ECO implementation. You will collaborate closely with cross-functional synthesis, physical design, and verification squads in Agile sprint cycles while ensuring rigorous timing convergence. Furthermore, you will manage application requirements by submitting your updated professional profile via direct email to Lakshmi L at [e-mail].

Key Responsibilities

• Execute rigorous Static Timing Analysis (STA) and timing signoff for complex ASIC and System-on-Chip (SoC) semiconductor designs.
• Perform advanced setup, hold, and recovery/removal timing analysis and closure utilizing Synopsys PrimeTime.
• Develop, validate, and optimize SDC timing constraints for high-speed digital integrated circuits.
• Analyze complex timing concepts including clock skew, clock latency, uncertainty, and clock domain crossing (CDC) considerations.
• Debug timing violations, analyze critical paths, and execute advanced timing optimization techniques.
• Perform Multi-Mode Multi-Corner (MMMC) analysis, signoff validation, false path analysis, and multicycle path definitions.
• Coordinate closely with physical design (PD) teams to provide timing closure support and implement Engineering Change Orders (ECO).
• Maintain comprehensive timing reports, constraint documentation, and signoff sign-off audit logs.

Required Qualifications & Skills

• Bachelor’s or Master’s degree in Electronics Engineering, VLSI Design, Electrical Engineering, or related technical discipline.
• Minimum of 4+ years of progressive professional experience in semiconductor engineering, ASIC design, and Static Timing Analysis (STA).
• Strong, demonstrable hands-on professional expertise with Synopsys PrimeTime for timing analysis and signoff verification.
• Comprehensive working knowledge and practical proficiency in SDC timing constraints development and validation.
• Deep practical experience in MMMC (Multi-Mode Multi-Corner) analysis, false paths, multicycle paths, and generated clocks.
• Solid practical grasp of synthesis, physical design (PD), and the complete ASIC design lifecycle.
• Proven expertise in timing closure support, ECO implementation, and critical path debugging.
• Mandatory legal work eligibility and physical availability for professional operations in Bangalore or Hyderabad.

Nice-to-Have Skills

• Professional certifications in VLSI design, advanced STA methodologies, or EDA tool specializations.
• Prior professional working experience in top-tier semiconductor product companies, ASIC design houses, or IP development firms.
• Hands-on familiarity with advanced process nodes (7nm, 5nm, 3nm) and low-power design techniques (UPF/CPF).
• Experience utilizing scripting languages such as Tcl, Python, or Perl for timing automation and report parsing.
• Exposure to agile semiconductor project management methodologies and enterprise tracking platforms (Jira, Confluence).

Application Information

• Recruiter: Logicsemi Technologies Recruitment Division
• Contact Name: Lakshmi L
• Email: [e-mail]
• Phone:
• Company Website: https://www.logic-semi.com
• Salary/Rate: Market Competitive / Enterprise Semiconductor Package
• Deadline: Open until filled (Urgent Bangalore/Hyderabad STA Opening)
• Notice Period: Immediate to 30 Days Preferred
• Contract Duration: Permanent / Full-Time Engagement (Bangalore / Hyderabad)