Staff Engineer, Physical Design - Caches

SiFive; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

SiFive is seeking a Staff Physical Design Engineer (Caches/Memory Subsystems) to own the physical implementation from RTL to GDSII. You will deliver high-performance, dense, and power-efficient memory designs on advanced and legacy process nodes.

You will collaborate across design layers, optimize PPA, and work with RTL designers, IP vendors, and power teams to ensure efficient integration of memory instances.

Qualifications

• 7+ years in physical design implementation of PPA critical blocks (CPUs, Caches).
• Strong understanding of digital logic and basic memory architecture.
• Proven ability to optimize for aggressive PPA targets with standard techniques.
• Hands-on RTL-to-GDSI implementation with Synopsys/Cadence flows and scripting.

Responsibilities

• Own cache implementation: drive physical design for high-performance blocks; manage S&P and sign-off.
• Collaborate across Architecture/RTL/Implementation to resolve physical bottlenecks.
• Address memory-specific challenges: dense SRAM placement, complex routing, timing through memory arrays.
• Optimize block-level implementation for Power, Performance, and Area goals.
• Work with RTL designers, IP vendors, and power teams to integrate memory instances.

Skills

Physical design

PPA optimization

RTL understanding

Scripting

Cadence/Synopsys tools

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Synthesis

Place & Route

Sign-off tools

Job description

About the Role

As a Staff Physical Design Engineer (Caches/Memory Subsystems) at SiFive, you will own the physical implementation of critical memory cache structures and tightly integrated SRAM subsystems, from RTL to GDSII. You will deliver high-performance, dense, and power‑efficient memory designs on advanced and legacy process nodes. Your primary focus will be physical design, but you will also collaborate across design‑abstraction layers to act as a bridge between architecture, RTL, and implementation teams.

Responsibilities

• Own Cache Implementation: Drive the physical design implementation for high-performance cache blocks and memory subsystems, managing synthesis, place & route, and sign‑off.
• Engage in Cross‑Abstraction‑Layer Co‑Design: Actively participate in Architecture/RTL/Implementation co‑design, suggesting RTL tweaks, pipeline strategies, or custom macro arrangements to resolve physical bottlenecks.
• Solve Memory‑Specific Challenges: Tackle physical bottlenecks unique to cache design, including dense SRAM macro placement, complex routing over macros, critical‑path timing through memory arrays, and strict dynamic/leakage power management.
• Aggressive PPA Optimization: Optimize block‑level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex trade‑offs for various product lines.
• Collaborate Cross‑Functionally: Work closely with RTL designers, IP vendors, and power teams to close design requirements and ensure efficient integration of memory instances.
• Enhance Methodology: Support and improve physical design flows, automation scripts, and methodologies for memory‑heavy block implementation.

Requirements

• 7+ years of hands‑on experience in physical design implementation of PPA critical blocks (CPUs, Caches, etc.).
• Solid understanding of digital logic design and basic memory architecture; comfortable reading RTL to understand design intent.
• Proven ability to optimize for aggressive PPA targets using industry‑standard physical design techniques.
• Hands‑on knowledge of RTL‑to‑GDS implementation with Synopsys and/or Cadence synthesis, PnR, and sign‑off tools, along with scripting skills.
• Education: Bachelor’s or Master’s in Electrical or Computer Engineering.

Why Join Us

• Be part of the RISC‑V movement and help define the future of computing architecture.
• Work on industry‑leading IP adopted by top customers and shipped in high volumes worldwide.
• Collaborate with world‑class engineers in a supportive, fast‑paced, learning environment.
• Enjoy a culture that values innovation, ownership, and technical excellence.
• Opportunities to engineer solutions across multiple IP families over time.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.