Staff Engineer, Physical Design - Cores

SiFive India Private Limited; Bengaluru; On-site; INR 1,800,000 - 2,500,000; Full time

Job summary

SiFive India Private Limited is looking for a Staff Physical Design Engineer to lead the physical implementation of high-performance CPU core blocks. The role involves collaboration across architecture, RTL design, and power teams to optimize for performance, power, and area (PPA) goals.

With over 7 years of experience in physical design and strong expertise in CPU design, you will drive implementations and solve physical bottlenecks, enhancing methodologies to meet high-frequency targets.

Qualifications

• 7+ years of hands-on experience in physical design implementation.
• Experience with complex control logic and execution units.
• Solid understanding of processor microarchitecture.

Responsibilities

• Drive the physical design implementation for high-frequency CPU core blocks.
• Collaborate with CPU architecture, RTL design, and Power teams.
• Optimize block-level implementation for aggressive PPA goals.

Skills

Physical design implementation

CPU design

Problem solving

Collaboration

Detail oriented

Tool proficiency

Education

Bachelor’s or Master’s in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Job description

Job Description

At SiFive, we’re redefining the compute landscape with our industry-leading RISC‑V compute platforms. As a Staff Physical Design Engineer (CPU Cores), you will own the physical implementation of critical, high‑performance processor core blocks from RTL to GDSII.

Responsibilities

• Own Core Implementation: Drive the physical design implementation for high‑frequency CPU core blocks and execution pipelines, managing synthesis, place‑&route, and signoff.
• Engage in Cross‑Abstraction‑Layer Co‑Design: Actively collaborate with Architecture, RTL, and Power for PPA co‑optimisation; understand the CPU microarchitecture to identify logic‑depth bottlenecks early and suggest RTL pipelining strategies or structural changes.
• Solve Core‑Specific Challenges: Tackle physical bottlenecks unique to CPU cores, including timing closure, datapath placement, routing congestion, complex clock tree synthesis (CTS) for high‑speed pipelines, and rigorous dynamic power optimisation.
• Aggressive PPA Optimization: Optimize block‑level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex PPA trade‑offs to meet target frequencies across various product lines.
• Collaborate Cross‑Functionally: Work closely with CPU architecture, RTL design, and Power teams to close design requirements and ensure efficient physical realization of the instruction set architecture.
• Enhance Methodology: Support and improve physical design flows, automation scripts, and methodologies tailored specifically for high‑frequency, complex core implementation.

Requirements

• 7+ years of hands‑on experience in physical design implementation with a proven track record of block‑level tape‑outs involving high‑speed digital logic like CPUs.
• CPU/Datapath Expertise: Experience implementing complex control logic, execution units (ALUs, FPUs), or custom data‑paths; familiarity with physical challenges of pushing high‑frequency design limits.
• Cross‑Abstraction Awareness: Solid understanding of processor microarchitecture (e.g., instruction pre‑fetch, execution units, data forwarding paths) and ability to read RTL to understand design intent.
• Strong Problem Solving: Proven ability to optimise for aggressive PPA targets using industry‑standard physical design techniques, with a detail‑oriented mindset and clear communication of results.
• Tool Proficiency: Hands‑on knowledge of RTL‑to‑GDS implementation with Synopsys and/or Cadence implementation and sign‑off tools.
• Education: Bachelor’s or Master’s in Electrical or Computer Engineering.

Location & Eligibility

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

Equal Opportunity

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Why Join Us?

Be part of the RISC‑V movement and help define the future of computing architecture. Work on industry‑leading IP adopted by top customers and shipped in high volumes worldwide. Collaborate with world‑class engineers in a supportive, fast‑paced, learning environment. Enjoy a culture that values innovation, ownership, and technical excellence.