Staff Engineer, Physical Design - Caches

SiFive India Private Limited; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

SiFive India Private Limited is looking for a Staff Physical Design Engineer to enhance memory cache structures. The role demands expertise in physical design implementation and optimization for high-performance cache blocks, solving memory-specific challenges, and collaborating cross-functionally.

The ideal candidate will have 7+ years of experience and a strong grasp of digital logic and memory architecture. We celebrate diversity and foster an inclusive work environment.

Qualifications

• 7+ years of hands-on experience in physical design implementation of PPA critical blocks.
• Solid understanding of digital logic design and basic memory architecture.
• Proven ability to optimize for aggressive PPA targets using industry-standard techniques.
• Hands-on knowledge of RTL to GDS implementation with relevant tools.

Responsibilities

• Drive physical design implementation for high-performance cache blocks.
• Participate in Architecture/RTL/Implementation co-design.
• Optimize block-level implementation for Power, Performance, and Area goals.
• Collaborate with RTL designers and power teams.

Skills

Physical design implementation

Digital logic design

Problem-solving for PPA

Scripting skills

Education

Bachelor’s or Master’s in Electrical or Computer Engineering

Tools

Synopsys tools

Cadence tools

Job description

Job Description

About the Role – At SiFive, we’re redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Staff Physical Design Engineer (Caches/Memory Subsystems), you will own the physical implementation of critical memory cache structures and tightly integrated SRAM subsystems, from RTL to GDSII. You will deliver high-performance, dense, and power-efficient memory designs on advanced and legacy process nodes. While your primary focus will be in physical design, we are looking for engineers capable of operating across design‑abstraction layers. Caches are the heart of CPU performance, and you will act as a bridge between the architecture, RTL, and implementation teams. By understanding the underlying design, you will help drive co‑design optimizations that directly impact the speed, area, and efficiency of our IP.

Responsibilities

• Own Cache Implementation: Drive the physical design implementation for high-performance cache blocks and memory sub-systems, managing synthesis, place & route, and signoff.
• Engage in Cross‑Abstraction‑Layer Co‑Design: Go beyond standard implementation by actively participating in Architecture/RTL/Implementation co‑design. Understand the cache micro‑architecture to suggest RTL tweaks, pipeline strategies, or custom macro arrangements etc. that resolve physical bottlenecks.
• Solve Memory‑Specific Challenges: Tackle physical bottlenecks unique to cache design, including highly dense SRAM macro placement, complex routing over macros, critical‑path timing through memory arrays, and strict dynamic/leakage power management.
• Aggressive PPA Optimization: Optimize block‑level implementation for aggressive Power, Performance, and Area (PPA) goals, managing complex trade‑offs for various product lines.
• Collaborate Cross‑Functionally: Work closely with RTL designers, IP vendors, and power teams to close design requirements and ensure efficient integration of memory instances.
• Enhance Methodology: Support and improve physical design flows, automation scripts, and methodologies for memory‑heavy block implementation.

Requirements

• 7+ years of hands‑on experience in physical design implementation of PPA critical blocks (CPUs, Caches etc.).
• Cross‑Abstraction Awareness: A solid understanding of digital logic design and basic memory architecture. Comfortable reading RTL to understand the design intent and collaborate effectively with front‑end teams.
• Strong Problem‑Solving: Proven ability to optimize for aggressive PPA targets using industry‑standard physical design techniques, accompanied by a detail‑oriented mindset.
• Tool Proficiency: Hands‑on knowledge of RTL to GDS implementation with Synopsys and/or Cadence synthesis, PnR and signoff implementation tools, and good scripting skills.
• Education: Bachelor’s or Master’s in Electrical or Computer Engineering.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, that we can successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.