Staff Engineer

SiFive, Inc.; Bengaluru; On-site; INR 2,500,000 - 5,500,000; Full time

Job summary

SiFive, Inc. is seeking a senior DV engineer to advance CPU verification using SystemVerilog and UVM. The role involves crafting targeted tests for RISCV cores and leveraging internal test generators to improve coverage and test plans.

The candidate should have deep knowledge of CPU architectures (x86/ ARM/ RISCV), strong Python scripting skills, and experience with bus interfaces like AXI/ PCIe. On-site in India is expected with rigorous background checks.

Qualifications

• 7–12 years of DV experience in CPU verification.
• Proficiency in SystemVerilog and UVM.
• Experience with x86/ ARM/ RISCV architectures and test planning.
• Python scripting is a plus.

Responsibilities

• Hands on system Verilog/UVM development for modern high-performance CPU verification.
• Write test cases and use test generators to generate targeted tests for RISCV CPU verification.
• Collaborate with teams to target coverage and test-plan scenarios.

Skills

SystemVerilog

UVM

OO programming

CPU architectures

Python scripting

AXI/PCIe

VIP integration

Test case writing

Education

Bachelor's degree

Master's degree

Tools

Test generators

VIP integration tools

SystemVerilog simulators

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsiteandGlassdoorpages.

Job Description:

Responsibilities:

• Hands on system Verilog/UVM development work for modern high performance CPU verification.

• Work will involve writing test cases, using test generators to generate targeted tests for RISCV CPU verification.

• Working with internal test generators to target coverage/test-plan scenarios.

Requirements:

• 7-12 years of experience in DV preferably in CPU verification with a bachelor’s or master’s degree.

• Proficiency in System Verilog and UVM methodology.

• Very good object-oriented programming skills.

• Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.

• Any scripting knowledge, preferably python.

• Bus interface knowledge like AXI or PCIE

• Integration experience with third party VIPs like bus VIPs.

• CPU micro-arch knowledge.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.