Staff Verification Engineer - Security Blocks

SiFive, Inc.; Bengaluru; On-site; INR 4,200,000 - 7,000,000; Full time

Job summary

SiFive, Inc. in Bengaluru seeks an experienced Verification Engineer to join our CPU DV team. You will define verification strategies, develop scalable testbenches with SystemVerilog and UVM, and collaborate with RTL and software groups to ensure IP quality.

The ideal candidate has 7–12 years in DV, strong SystemVerilog/UVM skills, object‑oriented programming, scripting in Python/Perl, and knowledge of AXI/PCIE bus interfaces and CPU architectures (x86/ARM/RISC-V).

Qualifications

• 7–12 years of experience in DV preferably in CPU verification with a Bachelor’s or Master’s in Engineering.
• Proficiency in System Verilog and UVM methodology.
• Very good object-oriented programming skills.
• Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.
• Any scripting knowledge, preferably python.
• Bus interface knowledge like AXI or PCIE
• Integration experience with third party VIPs like bus VIPs.
• CPU micro-arch knowledge.

Responsibilities

• Verification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.
• Testbench Development: Design and implement scalable, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Stimulus & Constraint Generation: Write complex sequences and constrained-random tests to stress-test the IP across corner cases.
• Debugging: Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).
• Coverage Closure: Define and track functional and code coverage metrics. Write covergroups and coverpoints to ensure all architectural features have been exercised.
• Must know the RISC-V spec and processor-based verification and knowing risc-v security architecture is highly preferable.
• Languages : SystemVerilog, Verilog, Python/Perl (scripting), C/C++
• Methodologies UVM (highly preferred), OVM, or VMM
• Protocols AXI,AHB, Security architecture

Skills

SystemVerilog

UVM

Python

Perl

C/C++

Verilog

Object-oriented programming

Education

Bachelor’s or Master’s in Engineering

Tools

Verdi

SimVision

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsiteandGlassdoorpages.

Job Description:

Core Responsibilities

• Verification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.

• Testbench Development: Design and implement scalable, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).

• Stimulus & Constraint Generation: Write complex sequences and constrained-random tests to stress-test the IP across corner cases.

• Debugging: Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).

• Coverage Closure: Define and track functional and code coverage metrics. Write covergroups and coverpoints to ensure all architectural features have been exercised.

• Must know the RISC-V spec and processor-based verification and knowing risc-v security architecture is highly preferable.

• Languages : SystemVerilog, Verilog, Python/Perl (scripting), C/C++

• Methodologies UVM (highly preferred), OVM, or VMM

• Protocols AXI,AHB, Security architecture

Requirements:

• 7-12 years of experience in DV preferably in CPU verification with a Bachelor’s or Master’s in Engineering

• Proficiency in System Verilog and UVM methodology.

• Very good object-oriented programming skills.

• Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.

• Any scripting knowledge, preferably python.

• Bus interface knowledge like AXI or PCIE

• Integration experience with third party VIPs like bus VIPs.

• CPU micro-arch knowledge.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.