Senior Engineer - Hardware Engineering - DV

SiFive India Private Limited; Ahmedabad District; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

SiFive India Private Limited is seeking a hands-on DV engineer to contribute to high‑performance CPU verification using SystemVerilog and UVM. You will write test cases, leverage internal test generators, and help shape verification coverage plans for RISCV CPUs.

Candidates should have 3 years of CPU verification DV experience, strong SystemVerilog/UVM skills, knowledge of CPU architectures (RISC‑V, ARM, x86), scripting in Python, and familiarity with AXI/PCIe and third‑party VIPs.

Qualifications

• 3 years of experience in DV preferably in CPU verification.
• Proficiency in System Verilog and UVM methodology.
• Very good object‑oriented programming skills.
• Any CPU architecture knowledge (x86, ARM or RISC‑V) with test writing/test plan implementation experience.
• Any scripting knowledge, preferably python.
• Bus interface knowledge like AXI or PCIE.
• Integration experience with third‑party VIPs like bus VIPs.
• CPU micro-arch knowledge.

Responsibilities

• Hands on SystemVerilog/UVM development for high‑performance CPU verification.
• Write test cases and use test generators to target coverage/test‑plan scenarios for RISCV CPU verification.

Skills

SystemVerilog

UVM

Object oriented programming

Python scripting

CPU verification

Test writing

Tools

AXI

PCIe / PCIe bus

VIP integration

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data‑intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimise and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data centre, mobile and consumer. With SiFive, the future of RISC‑V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are. Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

Job Description

Responsibilities: Hands on system Verilog/UVM development work for modern high performance CPU verification. Work will involve writing test cases, using test generators to generate targeted tests for RISCV CPU verification. Working with internal test generators to target coverage/test‑plan scenarios.

Requirements: 3 years of experience in DV preferably in CPU verification. Proficiency in System Verilog and UVM methodology. Very good object‑oriented programming skills. Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience. Any scripting knowledge, preferably python. Bus interface knowledge like AXI or PCIE. Integration experience with third‑party VIPs like bus VIPs. CPU micro-arch knowledge.

Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in India. Any offer of employment for this position is also contingent on the Company verifying that you are an authorised for access to export‑controlled technology under applicable export control laws or, if you are not already authorised, our ability to successfully obtain any necessary export licence(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. Championed by leaders who chose to make a real difference, SiFive led the RISC‑V revolution—creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all. Now that we’ve made history, you have the opportunity to write the future.