Sr Staff Engineer - Physical Design

Synopsys Inc; Hyderabad; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Synopsys Inc. seeks an experienced ASIC physical design engineer to own end-to-end PD for UCIe PHY blocks and testchips.

You will drive synthesis, place-and-route, timing closure, and physical verification across multiple projects, collaborating with verification, DFT, and IP teams to resolve issues and meet aggressive PPA targets. You will mentor peers and influence floorplan decisions to ensure successful tapeouts.

Qualifications

• 7+ years of hands-on experience in ASIC physical design.
• Experience delivering tapeouts to GDSII for advanced nodes.
• Proficiency with industry-standard tools (DC, PT, ICC2/FC, ICV).
• Record of signoff ownership on SoC/IP tapeouts.

Responsibilities

• Own physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and beyond.
• Drive synthesis, place & route, timing closure, and physical verification across multiple concurrent projects.
• Collaborate with verification, DFT, and IP teams to resolve issues and meet PPA targets without schedule slips.
• Lead design reviews, present tradeoffs, and decide floorplan, clock tree, and signoff actions.

Skills

ASIC physical design

Synthesis

Place & route

Timing closure

Physical verification

GDSII

Signoff

Tools

DC

PrimeTime/PT

ICC2/FC

ICV

Job description

Job Description:

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

What You'll Be Doing

• Own physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes
• Drive synthesis, place and route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across multiple concurrent projects
• Work directly with verification, DFT, and IP integration teams to resolve design issues, close timing, and meet PPA targets without slipping the schedule
• Lead design reviews, present tradeoff analyses, and make real-time decisions on floorplan changes, clock tree strategies, and signoff waivers
• Pilot new physical design flows and advanced node methodologies, then document what worked and what did not for the rest of the team
• Mentor junior engineers on timing closure techniques, physical verification strategies, and how to navigate the ICC2 toolchain effectively
• Interface with foundry partners and customer engineering teams to resolve technology file issues, DRC/LVS challenges, and silicon bring-up questions

The Impact You Will Have

• Deliver production-quality UCIe PHY designs that enable next-generation chip-to-chip connectivity for Synopsys customers building AI accelerators, data center processors, and high-performance compute systems
• Improve design cycle time and PPA outcomes by driving tooling and methodology improvements across the physical design flow that the entire IP team will adopt
• Handle multiple concurrent tapeouts in leading-edge technologies, ensuring Synopsys meets customer commitments and maintains its reputation for on-time silicon delivery
• Strengthen customer confidence in Synopsys IP through high-quality signoff, responsive technical engagement during integration, and designs that actually work in silicon
• Influence product roadmap decisions by surfacing design insights and PPA tradeoffs that matter to end customers during architecture and planning phases
• Contribute to how Synopsys approaches physical design for 3nm and beyond by piloting new flows, feeding lessons learned back into the methodology team, and shaping best practices
• Enable faster time-to-market for customers by delivering UCIe IP that integrates cleanly, meets timing out of the box, and requires minimal rework during SoC integration

What You'll Need

• 7+ years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification
• Multiple tapeouts and signoffs in 5nm or more advanced process nodes, you have taken designs all the way to GDS and dealt with the messiness that comes with it
• Proficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV, you know the commands, the flow, and the workarounds
• Proven track record working on SoC or IP tapeouts where you owned significant portions of the physical design and were accountable for signoff
• Strong understanding of FinFET technology and the physical design challenges specific to advanced nodes, including multi-patterning, electromigration, and IR drop at scale
• Experience with DFT insertion, scan chain routing, and ATPG is a strong plus, especially if you have debugged DFT-related timing or physical issues
• Exposure to UCIe, SerDes, or high-speed interface IP is valuable but not required, we care more about your physical design depth and ability to learn quickly

Who You Are

• You can walk into a timing review with 500 failing paths and know within ten minutes which ones actually matter and which ones are tool artifacts or false paths
• You are comfortable making tradeoff calls under pressure, like choosing to upsize a cell and take the area hit because you know the timing margin is real and the schedule cannot slip
• You do not need someone to tell you what to do next, when floorplan is done, you move to placement, when placement converges, you start clock tree, and you flag blockers before they become emergencies
• You can explain a complex physical design issue to an architect or a customer engineer in two sentences without losing the technical nuance that matters
• You have mentored junior engineers before, not in a formal program, but because someone asked you a question and you took the time to show them the right way instead of just giving them the answer
• You are organized enough to manage three tapeouts at different stages without dropping details, and you know how to keep stakeholders informed without over-communicating

The Team You'll Be Part Of

You will be part of an engineering team dedicated to implementing UCIe PHY and testchips. The team focuses on the full physical design flow, encompassing synthesis, physical design, verification, design for test, and ATPG. You will collaborate with both internal and external design teams, contributing to complex projects and driving technological innovation in advanced connectivity IP.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.