Principal ASIC Implementation Engineer

Synopsys Inc; Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Benefits offered by this job

Comprehensive health benefits

Wellness programs

Financial benefits packages

Job summary

Synopsys Inc is looking for an expert in ASIC physical design to develop and deliver scalable CAD reference flows for cutting-edge Interface IP. With over 15 years of experience required, you will collaborate with teams across the globe, working on advanced technology nodes such as 5nm, 3nm, and 2nm.

This position demands strong knowledge of Synopsys EDA tools, and your leadership will help ensure successful tapeouts and time-to-market efficiency for our innovative semiconductor solutions.

Qualifications

• 15+ years of hands-on experience in ASIC physical design or CAD flow development.
• Deep expertise across the entire physical implementation flow.
• Strong working knowledge of Synopsys EDA tools in production environments.
• Proficiency in Perl and Tcl scripting for automation.

Responsibilities

• Develop scalable CAD reference flows for Synopsys Interface IP.
• Collaborate with IP R&D teams to validate new features.
• Provide technical support during critical test-chip tapeouts.
• Drive timing closure and IR drop analysis for complex designs.

Skills

ASIC physical design

CAD flow development

Automation with Perl

Automation with Tcl

Communication

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Science

Tools

Synopsys Design Compiler

PrimeTime

Fusion Compiler

ICC2

ICV

RedHawk

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry‑leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent over fifteen years in physical design, and you know the difference between a clean tapeout and weeks in ECO hell comes down to decisions made during floorplanning. You have lived through enough node transitions to anticipate what breaks when moving from 7nm to 3nm before it happens.

You think in flows, not just tools. A timing report tells you what it means for routing congestion, IR drop, and whether a customer can close their derivative. You build CAD flows that other engineers actually want to use because adoptability matters as much as results.

Working with R&D does not intimidate you. You push back when a feature misses the real problem and collaborate when it solves one. You can sit with an IP designer in Bangalore, a field engineer in San Jose, and a customer in Seoul, and everyone walks away with clarity. At Synopsys, you will build the reference flows that define how our Interface IP gets implemented at the industry’s most advanced nodes.

What You’ll Be Doing

• Develop and deliver scalable CAD reference flows for Synopsys Interface IP across 5nm, 3nm, and 2nm nodes using Fusion Compiler, ICC2, DC, PrimeTime, ICV, and RedHawk
• Collaborate directly with IP R&D teams to influence product roadmaps, validate new features, and ensure our tools and IP work together to deliver differentiated PPA
• Demonstrate best‑in‑class power, performance, and area results on industry‑standard Interface IP protocol designs that customers use to benchmark our solutions
• Provide hands‑on technical support to IP developers, field application engineers, and customers during critical test‑chip tapeouts at leading‑edge nodes
• Automate flow development and optimization using Perl and Tcl scripting to reduce manual effort and improve consistency across IP families
• Drive timing closure, IR drop analysis, EM verification, and physical sign‑off for complex designs, ensuring flows are robust enough for high‑volume adoption
• Stay ahead of process technology shifts and EDA tool updates, continuously refining methodologies to address emerging challenges in advanced node implementation

The Impact You Will Have

• Your CAD flows will become the foundation that IP designers and customers rely on to achieve first‑pass success on multi‑million‑gate designs
• You will directly accelerate time‑to‑market for Synopsys Interface IP by delivering flows that are proven, documented, and ready to scale
• Your PPA demonstrations will shape how customers and field teams position Synopsys IP against competitive solutions in the most demanding applications
• The technical guidance you provide during tapeouts will help customers avoid costly respins and meet their own aggressive project timelines
• Your collaboration with R&D will influence the next generation of EDA tool features, ensuring they solve real implementation problems, not theoretical ones
• You will raise the quality bar across the IP portfolio by embedding best practices into flows that get reused across dozens of products and nodes
• Your mentorship and technical leadership will strengthen the broader engineering team, building capability that outlasts any single project

What You’ll Need

• 15+ years of hands‑on experience in ASIC physical design or CAD flow development, with a proven track record on complex SoCs at 7nm and below
• Deep expertise across the full physical implementation flow including floorplanning, synthesis, place and route, timing closure, IR drop and EM analysis, and physical verification
• Strong working knowledge of Synopsys EDA tools including Design Compiler, PrimeTime, ICC2, Fusion Compiler, ICV, and RedHawk in production environments
• Demonstrated experience developing CAD flows or methodologies that have been adopted across multiple projects or product lines
• Proficiency in Perl and Tcl scripting for automation, flow integration, and result analysis
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience
• Experience with advanced Interface IP protocols such as PCIe, DDR, USB, or similar high‑speed standards is a strong plus

Who You Are

• You can walk into a room where timing is failing by 500ps and within an hour identify whether the problem is in the floorplan, the constraints, the synthesis strategy, or the IP itself
• You write flows and scripts that other engineers can actually read and modify six months later without needing you in the room
• You know when to escalation a tool issue to R&D and when to work around it, and you do not waste time fighting battles that do not move the design forward
• You communicate tradeoffs clearly, whether you are talking to an IP architect about a design decision or a customer about why their peace of your PPA target requires a different approach
• You manage multiple parallel efforts without losing track of details, and you know how to prioritize when three teams all need your input in the same week
• You mentor without micromanaging, and you build capability in the people around you because you know that scalable impact requires a strong team

The Team You’ll Be Part Of

Join a world‑class R&D organization at the forefront of IP subsystem innovation. Our multidisciplinary teams work across engineering, EDA tools, product management, and customer success to deliver solutions that power tomorrow’s intelligent systems. We value creativity, technical rigor, and excellence, providing an environment where every member can contribute and grow.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.