Sr. Staff Engineer, Front-End CAD / Design Automation

Ayar Labs; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Ayar Labs in Bengaluru, India seeks a Sr. Staff Front-End CAD / Design Automation Engineer to own the design automation flows for RTL through signoff and handoff. You will build scalable automation in Python/Tcl/Shell, deploy EDA tools, and drive CI/CD practices across teams.

Ideal candidates have 10+ years in ASIC CAD and a track record of production-quality automation, RPM/QA driven development, and mentoring across globally distributed teams. This role is on-site with flexible hours.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science or related technical field.
• 10+ years of experience in ASIC CAD, EDA flow automation, front-end methodology, or design automation.
• Strong scripting and automation experience in Python, Tcl, Shell, Make, and Linux/Unix environments.
• Hands-on experience with RTL, Verilog/SystemVerilog, lint, CDC/RDC, low power, simulation, synthesis setup, and constraints.
• Experience building production-quality automation used by multiple design teams.
• Strong debugging skills across tools, scripts, logs, environments, licenses, queues, and design setup.
• Strong communication skills and ability to drive methodology across cross-functional teams.

Responsibilities

• Own front-end CAD flows for RTL development, IP integration, design assembly, regressions, and signoff readiness.
• Develop and maintain automation for lint, CDC/RDC, low-power checks, reset checks, simulation setup, synthesis readiness, constraints, and release flows.
• Build scalable Python/Tcl/Shell/Make-based tooling for design configuration, dependency management, regression execution, reporting, dashboards, and flow orchestration.
• Support EDA tool deployment, environment setup, module integration, license awareness, tool-version qualification, and vendor debug across major EDA vendors.
• Define best practices for Git/GitLab-based design release, CI/CD, Jenkins regressions, workspace setup, reproducible project flows.
• Create metrics and reports for regression status, waiver tracking, design health, QoR, runtime, failures, resource usage, and signoff progress.
• Work with RTL, verification, physical design, DFT, firmware, and analog/mixed-signal teams to debug flow, tool, environment, license, queue, and design setup issues.
• Develop, deploy, and champion AI-assisted CAD workflows, agents, and templates to improve productivity and reliability.
• Define consistent automation patterns, prompts, templates, and workflow guardrails to maximize token efficiency.
• Mentor engineers on front-end CAD methodology, automation quality, and design handoff.

Skills

Python

Tcl

Shell

Make

Linux

Verilog

SystemVerilog

Front-end CAD

Design automation

CI/CD

Education

BS/MS in Electrical Engineering or Computer Engineering or Computer Science

Tools

Synopsys Cadence Siemens Mentor

Job description

Location: Bengaluru, India (on-site, flexible hours)

Ayer Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

Ayar Labs is transforming AI infrastructure by moving data at the speed of light. Our optical I/O technology enables higher bandwidth, lower power, and more scalable compute architectures for next-generation AI and HPC systems.

We are looking for a Sr. Staff Front-End CAD / Design Automation Engineer to own and scale the design automation flows used by our ASIC and SoC teams. This role will drive methodology, tools, infrastructure, and automation from RTL development through front-end signoff and physical-design handoff. This role will also help define how Ayar Labs uses AI-assisted engineering workflows: building repeatable agents, templates, and automation patterns that make design/CAD tasks faster, more consistent, token-efficient, and easier to review.

Essential Functions

• Own front-end CAD flows for RTL development, IP integration, design assembly, regressions, and signoff readiness.
• Develop and maintain automation for lint, CDC/RDC, low-power checks, reset checks, simulation setup, synthesis readiness, constraints, and release flows.
• Build scalable Python/Tcl/Shell/Make-based tooling for design configuration, dependency management, regression execution, reporting, dashboards, and flow orchestration.
• Support EDA tool deployment, environment setup, module integration, license awareness, tool-version qualification, and vendor debug across Synopsys, Cadence, Siemens EDA/Mentor, or similar tools.
• Define best practices for Git/GitLab-based design release, CI/CD, Jenkins regressions, workspace setup, reproducible project flows, and job schedulers such as Slurm, LSF, UGE, or similar.
• Create metrics and reports for regression status, waiver tracking, design health, QoR, runtime, failures, resource usage, and signoff progress.
• Work with RTL, verification, physical design, DFT, firmware, and analog/mixed-signal teams to debug flow, tool, environment, license, queue, and design setup issues.
• Develop, deploy, and champion AI-assisted CAD workflows, skills and agents that improve engineering productivity, reduce manual debug loops, and produce predictable, reviewable results.
• Define consistent automation patterns, prompts, templates, and workflow guardrails to maximize token efficiency and reliability across repeated design/CAD tasks.
• Mentor engineers on front-end CAD methodology, automation quality, and reliable design handoff.

Basic Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• 10+ years of experience in ASIC CAD, EDA flow automation, front-end methodology, or design automation.
• Strong scripting and automation experience in Python, Tcl, Shell, Make, and Linux/Unix environments.
• Hands-on experience with RTL, Verilog/SystemVerilog, lint, CDC/RDC, low power, simulation, synthesis setup, and constraints.
• Experience building production-quality automation used by multiple design teams.
• Strong debugging skills across tools, scripts, logs, environments, licenses, queues, and design setup.
• Strong communication skills and ability to drive methodology across cross-functional teams.

Preferred Qualifications

• Experience with SoC/IP integration, front-end signoff, UPF, GLS, timing simulation setup, DFT handoff, or advanced-node ASIC development.
• Experience deploying AI-assisted engineering workflows, internal agents, copilots, or automation assistants for design/CAD/verification teams.
• Ability to drive consistent methodology across globally distributed teams and mentor engineers through adoption.

Note To Recruiters

Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.