ASIC Digital Design, Sr Manager

Synopsys Inc; Dadri; On-site; INR 4,000,000 - 8,000,000; Full time

Benefits offered by this job

Health, wellness and financial rewards

Total rewards package

Job summary

Synopsys Inc in Noida seeks a senior verification leader with 15+ years in ASIC design to drive complex projects end-to-end, leading design and verification engineers and defining scalable UVM-based environments.

You will mentor engineers, coordinate with architects and VIP teams, push for rigorous verification and early issue detection before tapeout, and communicate clearly in English. This role requires ownership, prioritization, and a track record of delivering high-quality silicon.

Qualifications

• 15+ years in ASIC design and verification, with high-speed protocols experience.
• Proficiency in Verilog, VHDL, SystemVerilog for RTL design and testbenches.
• Experience building UVM-based verification environments and coverage analysis.
• Scripting skills in Bash, TCL, Perl, Python for automation and tooling.
• Track record mentoring engineers and delivering multiple complex projects.
• Ability to work through ambiguous requirements and manage timelines.

Responsibilities

• Lead a team of design and verification engineers in Noida, managing performance, growth, and day-to-day execution across multiple ASIC projects
• Own the verification strategy and environment architecture for complex, high-speed protocol designs, defining testplans and coverage models
• Drive technical decisions around verification flows, including SystemVerilog, UVM, behavioral modeling, and coverage-driven verification
• Collaborate with architects, RTL designers, and VIP teams to align on design intent and ensure functional correctness before tapeout
• Identify design gaps and propose corrective actions when functionality does not match requirements
• Reproduce and resolve customer-reported issues through deep technical analysis
• Continuously improve verification methodologies, tooling, and execution efficiency across the team

Skills

Leadership

ASIC design

Verilog

VHDL

SystemVerilog

UVM

Scripting (Bash, Python, TCL)

Mentoring

Project management

Tools

UVM

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the better part of your career building and verifying silicon that actually ships, not just passes simulation. You know that verification is where the real complexity lives, where assumptions break, and where a good engineer becomes a great one by catching the corner case no one thought to write down. Leading a team is not about delegation for you, it is about building engineers who think critically, ask the right questions, and take ownership of the hard problems. You have been in the room when a design looked perfect on paper but fell apart under real stimulus. That experience taught you to build verification environments that stress the design in ways the architect did not anticipate. Mentorship matters to you because you remember the engineers who shaped how you think, and you want to do that for others. Managing multiple projects does not overwhelm you because you have learned to prioritize what matters, push back when timelines do not match reality, and keep your team focused on the work that moves the needle. You are technical enough to review a testbench architecture and organizational enough to keep three projects on track without losing sight of the people doing the work. At Synopsys, you will lead verification for complex ASIC designs that power the products our customers build, and you will do it with a team that values depth, rigor, and getting it right.

What You'll Be Doing

• Lead a team of design and verification engineers in Noida, managing performance, growth, and day-to-day execution across multiple ASIC projects
• Own the verification strategy and environment architecture for complex, high-speed protocol designs, defining testplans and coverage models that catch real issues
• Drive technical decisions around verification flows, including SystemVerilog, UVM, behavioral modeling, and coverage-driven verification
• Work directly with architects, RTL designers, and VIP teams to align on design intent, resolve ambiguities, and ensure functional correctness before tapeout
• Identify design gaps and propose corrective actions when documented functionality does not match implementation or customer requirements
• Reproduce and resolve customer-reported issues through deep technical analysis, working backward from symptoms to root cause
• Continuously improve verification methodologies, tooling, and execution efficiency across the team

The Impact You Will Have

• Deliver functionally correct, high-performance silicon designs that ship to customers and power next-generation products
• Build a team culture where engineers grow technically, take ownership, and solve hard problems without waiting for perfect direction
• Reduce time-to-market by catching design issues early through rigorous verification and well-architected testbenches
• Strengthen cross-functional collaboration between design, architecture, and verification, ensuring alignment and reducing late-stage surprises
• Influence verification best practices across Synopsys, shaping how teams approach coverage, automation, and testbench design
• Resolve customer issues faster and more thoroughly, building trust and long-term partnerships
• Set the technical bar for what great verification looks like, raising the standard across projects and teams

What You'll Need

• 15+ years of hands-on experience in ASIC design and verification, with deep expertise in high-speed protocols and complex digital systems
• Strong proficiency in Verilog, VHDL, and SystemVerilog for RTL design and verification
• Proven experience building UVM-based verification environments, including testbench architecture, coverage analysis, and constraint-driven stimulus
• Solid scripting skills in BASH, TCSH, PERL, PYTHON, or TCL for automation, flow development, and productivity tooling
• Track record of managing and mentoring engineering teams, balancing technical leadership with people development
• Experience working through ambiguous requirements, incomplete specs, or shifting priorities without losing momentum

Who You Are

• You can review a verification plan and immediately spot what is missing, whether it is a corner case, a coverage gap, or an unrealistic timeline
• You give feedback that makes engineers better, not just feedback that checks a box during a review cycle
• You are comfortable saying no when a project plan does not match reality, and you can explain why in a way that moves the conversation forward
• You manage multiple projects without losing track of the details that matter, knowing when to dive deep and when to trust your team
• You write and communicate clearly in English, whether it is a technical document, a status update, or a difficult conversation with a stakeholder
• You adapt quickly when priorities shift, helping your team stay focused on what matters most without creating chaos

Rewards and Benefits

• We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
• Our total rewards include both monetary and non-monetary offerings.