SoC STA Timing Engineer Staff

Qualcomm; Chennai District; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Qualcomm India Private Limited is seeking a senior STA engineer with 7–10 years of relavant experience to lead timing analysis for multi-mode, multi-voltage designs in SoC and SubSystem contexts.

The role requires hands-on use of PrimeTime and Tempus, TCL/Perl/Python scripting, and collaboration across design, DFT, synthesis, technology, CAD and physical implementation teams. Strong knowledge of CTS, AOCV/POCV, and parasitic extraction is essential.

Qualifications

• 7–10 years of relavant experience required.
• STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem.
• Timing analysis and debugging across multiple PVT with PrimeTime/Tempus.
• Flow optimization: run STA flows and correlate Spice to STA results.
• Develop methodologies/tools for timing and automate STA/PD flows using TCL/Perl/Python.

Responsibilities

• Collaborate with design, DFT, synthesis, technology, CAD and physical implementation teams.
• Perform STA setup and signoff for multi-mode, multi-voltage designs.
• Validate timing across PVT conditions and diagnose issues.

Skills

STA fundamentals

AOCV/POCV

CTS & constraints

PrimeTime

Tempus

Scripting TCL

Scripting Python

Mentoring

Spice simulations

Education

Bachelor's degree in ECE/CS

Master's degree in ECE/CS

PhD in Engineering

Tools

ICC2

Innovus

Job description

Job Description:

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Job Description

• 7 to 10 years of relavant experience is a must
• STA Setup & Signoff: Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for SoC & SubSystem
• Timing Analysis & Debug: Validate and debug timing across multiple PVT conditions using tools like PrimeTime and Tempus.
• Flow Optimization: Run STA flows and correlate Spice to STA results.
• Methodology Development: Evaluate timing methodologies/tools across technology nodes and automate STA/PD flows using TCL/Perl/Python.
• Cross-Functional Collaboration: Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.
• Low-Power Techniques: Knowledge of clock gating, power gating, and multi-voltage designs.
• ECO Timing Flow: Handle timing ECOs (DMSA, tweaker, PrimeClosure) and logical equivalence checks (RTL to Netlist).

Required Skills

• Strong expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints.
• Hands-on experience with STA tools: PrimeTime, Tempus.
• Familiarity with ASIC back-end flows: ICC2, Innovus.
• Knowledge of signal integrity, cross-talk noise, and parasitic extraction.
• Scripting proficiency: TCL, Perl, Python.
• Mentoring junior engineers in different areas of timing flows and methodologies
• Understanding of Spice simulations: Hspice, FineSim, Monte Carlo analysis.

Preferred Experience

• Driving timing convergence at chip-level and hard-macro level.
• Exposure to RTL-to-GDSII flows.
• Good technical writing and communication skills for cross-team collaboration

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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