Sr Staff Design Engineer

Lattice Semiconductor; Maharashtra; On-site; INR 2,000,000 - 3,000,000; Full time

Benefits offered by this job

Comprehensive compensation and benefits program

Job summary

Lattice Semiconductor in Pune, India is seeking a Senior Staff Physical Design Engineer. This full-time role focuses on IP design and full‑chip integration, requiring 12+ years of physical design experience.

The ideal candidate will lead critical design aspects, ensuring robust design implementation and quality checks while fostering collaboration across teams. Strong proficiency in scripting and physical design tools is essential. A comprehensive compensation package and opportunities for growth within the team are offered.

Qualifications

• 12+ years of experience driving physical design activities of ASIC blocks and full chips.
• Experience with multiple tapeouts.
• Proficient in industry-standard physical design tools.

Responsibilities

• Implement and lead RTL-to-GDSII flow for complex designs.
• Drive physical design closure of key ASIC blocks and full chips.
• Ensure design quality through all physical design quality checks.

Skills

Physical design flow improvements

Scripting (Perl, Python)

Design closure for ASIC blocks

Collaboration with RTL and verification teams

Education

BS/MS/PhD in Electronics Engineering, Electrical Engineering, or Computer Science

Tools

Innovus

Genus

Tempus

Voltus

Calibre

Conformal

Job description

Job Summary

Lattice Semiconductor is seeking a Senior Staff Physical Design Engineer to join the hardware design team focused on IP design and full‑chip integration. This full‑time role is based in Pune, India, and offers an opportunity to contribute, learn, innovate, and grow within a dynamic team that designs programmable logic solutions for global customers.

Role Specifics

• Full‑time individual contributor position located in Pune, India.
• Implement and lead RTL‑to‑GDSII flow for complex designs.
• Lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, power‑planning, timing, and physical sign‑off.
• Experience with physical design sign‑off checks, including timing closure, EM/RV, and physical verification (DRC, LVS).
• Drive efficiency and quality of the physical design flow and methodology, collaborating with the internal EDA team and external tool vendors.
• Proficiency in scripting (Perl, Python, or similar) to improve design efficiency and develop methodology.
• Collaborate with RTL, DFT, verification, and full‑chip teams to ensure robust design implementation.
• Open to both teaching best‑known methods to an existing FPGA team and learning from the team about the complexities of highly programmable FPGA fabrics; this role requires strong educator and open‑minded student qualities.

Accountabilities

• Serve as a key contributor to FPGA design efforts.
• Drive physical design closure of key ASIC blocks and full chips, bringing best‑in‑class methodologies to achieve optimal power, performance, and area.
• Ensure design quality through all physical design quality checks and sign‑off.
• Develop strong relationships with worldwide teams.
• Mentor and develop strong partners and colleagues.
• Occasional travel as needed.

Required Skills

• BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent.
• 12+ years of experience driving physical design activities of ASIC blocks and full chips.
• Experience with multiple tapeouts.
• Proficiency in industry‑standard physical design tools such as Innovus, Genus, Tempus, Voltus, Calibre, Conformal, etc.
• Independent worker with demonstrated problem‑solving abilities.
• Proven ability to work with multiple groups across different sites and time zones.

Benefits

Lattice offers a comprehensive compensation and benefits program designed to attract, retain, motivate, reward, and celebrate the highest caliber employees in the industry.

Additional Information

This position requires successful background and reference checks and satisfactory proof of your right to work in India.

Applications are welcome from all qualified candidates.