Get a reply from this employer — a resume and cover letter tailored to exactly what they’re hiring for.
Infineon Technologies AG in Bengaluru seeks a seasoned SoC integration architect to own high-speed interface PHY integration, including LPDDR and Ethernet PHYs. You will define placement strategy, power delivery, reference clocks and electrical constraints in collaboration with PHY IP teams.
You will review architectures, perform SI simulations, sign off on floorplans and IO boundaries, and help ensure ISO 26262 alignment.
Own the SoC-level integration architecture for high-speed interface PHYs (LPDDR, Ethernet PHY, HSPHY) — defining placement strategy, power delivery, reference clock assignment, and electrical compliance requirements. Define and maintain the chip-level interface specifications that high-speed PHY IP teams must comply with, including jitter budgets, termination requirements, and signal integrity constraints. Serve as the primary SoC architecture interface to PHY IP teams and external PHY vendors — driving integration feasibility assessments and resolving chip-level signal integrity issues. Perform or oversee early signal integrity simulation and parasitic analysis for high-speed interface regions of the chip. Review and provide architectural sign-off on PHY IP integration results, floorplan proposals, and high-speed IO region design decisions. Maintain technical architecture documentation in compliance with ISO 26262 requirements. Drive datasheet content for high-speed interface electrical parameters in collaboration with IP teams and customers.
Bachelor's or Master's degree in Electrical Engineering or related field. At least 10 years of industry experience in semiconductor development with proven experience in high-speed interface architecture or integration. Strong knowledge of high-speed interface PHYs — LPDDR memory PHY, Ethernet PHY, and high-speed serial interfaces (HSPHY/SerDes). Experience with chip-level signal integrity, jitter budgets, and eye diagram analysis for high-speed interfaces. Understanding of PHY placement constraints, power delivery requirements, and reference clock architecture for high-speed interfaces. Familiarity with IO ring architecture and ESD protection strategy at high-speed IO boundaries. Familiarity with ISO 26262 documentation standards. Pro-active collaborative attitude with strong communication skills in a global multi-cultural team. Fluent English required; German is a plus. Owned chip-level integration architecture for LPDDR, Ethernet PHY, or high-speed SerDes in a previous SoC program. Defined jitter budgets, power delivery specs, and placement constraints for high-speed PHYs at the SoC level. Worked with PHY IP vendors to establish interface specifications, simulation models, and integration acceptance criteria. Experience distinguishing SoC-level integration constraints from IP-internal design decisions — and driving the former without dictating the latter. Contributed to datasheet electrical parameters for high-speed interface sections.
WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply.