Soc Design Verification Director

Astera Labs; Bengaluru; On-site; INR 3,500,000 - 5,000,000; Full time

Job summary

Astera Labs in Bengaluru is looking for a Director of SoC Design Verification with over 20 years of experience. This leadership role involves defining verification strategies and overseeing complex designs across compute, networking, and storage domains.

The ideal candidate will possess deep expertise in SoC-level verification and UVM-based test plans. You will work with a talented engineering team to influence next-gen product strategies and foster innovation.

Qualifications

• 20+ years of experience in design verification, leading teams and delivering complex SoC/silicon products.
• Deep expertise in SoC-level verification, including interconnect fabrics and coherency protocols.
• Strong background in writing assertions and coverage analysis.

Responsibilities

• Own and drive the end-to-end SoC verification methodology.
• Lead and mentor a diverse team of engineers.
• Collaborate with multiple teams to optimize SoC-level verification.

Skills

Design verification

UVM-based test plan development

SoC-level verification

Team leadership

Education

Bachelor’s degree in Electrical or Computer Engineering

Master’s preferred

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Title

Director of SoC Design Verification

Overview

We are seeking a seasoned Director of SoC Design Verification with 20+ years of experience to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.

Key Responsibilities

• Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.
• Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.
• Guide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols.
• Champion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.
• Collaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.
• Represent verification in executive reviews, customer engagements, and industry forums.
• Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
• Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.
• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

Required Experience

• Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, HSIO, and peripherals.
• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
• Strong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels.
• Experience in developing scalable verification infrastructures to simplify and accelerate SoC-level deployments.

Preferred Experience

• Expertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies.
• Experience with buffering, queuing, QoS, and system-level performance analysis.
• Familiarity with emulation, FPGA prototyping, and hybrid verification flows.
• Knowledge of AI-driven verification methodologies and workforce transformation strategies.
• Experience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs.
• Familiarity with low-power verification methodologies and power-aware verification.

Why Join Us

• Opportunity to lead cutting-edge SoC development programs.
• Influence verification strategy across next-generation products.
• Build and grow a world-class verification organization.
• Work with highly talented engineering teams on innovative technologies.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.