Principal Logic Design Engineer

Astera Labs; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Astera Labs, a NASDAQ-listed company, is seeking a Principal Logic Design Engineer in Bengaluru to lead RTL/microarchitecture development for complex connectivity IP/subsystems. The role requires ownership across architecture, RTL implementation, integration, and silicon bring-up, with responsibilities spanning verification collaboration and post-silicon analysis.

The candidate will drive performance, latency, area, and power optimizations and mentor senior engineers.

Qualifications

• Experience designing complex connectivity IPs such as PCIe, UALink, Ethernet, CXL, and UCIe.
• Strong RTL/microarchitecture and SystemVerilog/Verilog skills.
• Deep understanding of high‑speed data paths, FIFOs, arbitration, flow control and error handling.

Responsibilities

• Lead RTL/microarchitecture development for complex connectivity IP/subsystems.
• Translate specifications and system requirements into robust hardware architecture.
• Design high-performance and scalable logic for controllers/subsystems.
• Work across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration.
• Develop and review RTL using SystemVerilog/Verilog.
• Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
• Drive performance, latency, area, and power optimization.
• Collaborate with verification teams to develop verification strategies and debug complex failures.
• Work with SoC integration and physical design teams to ensure successful implementation.
• Lead technical reviews and mentor senior engineers.
• Support post-silicon debug and root-cause analysis.

Skills

PCIE

UALink

Ethernet

CXL

UCIe

PCIe architecture

High-speed data paths

Arbitration

Flow control

Debugging

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Principal Logic Design Engineer

Experience - 10+ years

Job Summary

We are seeking a Principal Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.

Key Responsibilities

• Lead RTL/microarchitecture development for complex connectivity IP/subsystems.
• Translate specifications and system requirements into robust hardware architecture.
• Design high-performance and scalable logic for controllers/subsystems.
• Work across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration as applicable to the role.
• Develop and review RTL using SystemVerilog/Verilog.
• Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
• Drive performance, latency, area, and power optimization.
• Collaborate with verification teams to develop verification strategies and debug complex failures.
• Work with SoC integration and physical design teams to ensure successful implementation.
• Lead technical reviews and mentor senior engineers.
• Support post-silicon debug and root-cause analysis.

Required Skills

• Extensive experience in complex connec t i vity IPs such as PCIE, UALink, Ethernet, CXL, UCIe.
• Deep knowledge of PCIe architecture and protocol.
• Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.
• Experience with simulation, lint, CDC, synthesis, and timing considerations.
• Strong debugging and problem-solving skills.

Preferred

• Experience of working in switching silicon.
• Experience of working on entire cycle from concept to silicon production.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.