Senior IP Design Verification Engineer

Google India Pvt Ltd; Bengaluru; Sur place; INR 4 500 000 - 7 500 000; Plein temps

Résumé du poste

Google India Pvt Ltd in Bengaluru seeks a Senior IP Design Verification Engineer for Google Cloud. You will verify complex TPU-based AI hardware, drive full verification life-cycle, and collaborate with design teams to ensure AI/ML performance and accuracy targets are met.

You will build constrained-random environments with SystemVerilog/UVM, develop verification plans, and close coverage gaps to enable reliable tape-outs in a hyperscale cloud context.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8 years of verification experience with RTL level using SystemVerilog or Specman/E for FPGA/ASICs.
• Experience in verification and debug of IP/subsystem/SoCs in networking domain (packet processing, bandwidth management, congestion control).
• Experience with IP components/interconnects such as microprocessor cores and memory subsystems.

Responsabilités

• Plan verification of digital design blocks and interact with design engineers to identify important scenarios.
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct blocks.
• Measure verification holes and progress toward tape-out.
• Create constrained-random verification environment using SystemVerilog and UVM.

Connaissances

RTL verification

SystemVerilog

Specman/E

IP/SoC verification

Networking IP

Formation

Bachelor's degree in EE/CE/CS or related field

Master's or PhD preferred (Electrical/Computer Engineering or CS)

Outils

Industry simulators

Revision control systems

Regression systems

UVM

Description du poste

Senior IP Design Verification Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.


• 8 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.


• Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, congestion control.


• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.


• Experience with industry-standard simulators, revision control systems, and regression systems.


• Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.


• Experience with the full verification life cycle.


• Excellent problem-solving and communication skills.


• Experience in verification and debug of IP/subsystem/SoCs in the networking domain such as packet processing, bandwidth management, congestion control.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.


• Identify and write all types of coverage measures for stimulus and corner-cases.


• Debug tests with design engineers to deliver functionally correct design blocks.


• Measure to identify verification holes and to show progress towards tape-out.


• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).

Experience Level Senior Level