SI/PI Engineer

Avalon Technologies; Bengaluru; On-site; INR 1,000,000 - 1,400,000; Full time

Job summary

Avalon Technologies in Bengaluru seeks a skilled Signal Integrity/Power Integrity specialist to drive SI/PI/EMI simulations for high-speed PCB assemblies. You will analyze impedance, reflections, crosstalk, TDR, timing, and transient responses using HFSS and SI-wave, and provide design recommendations.

Collaborate with schematic, layout, and mechanical teams to ensure SI/PI/EMC compliance with industry standards and deliver robust, manufacturable solutions.

Qualifications

• Experience in package level SI/PI simulation.
• Knowledge of ANSYS HFSS 3D and SI-wave for PI/SI/EMI simulations.
• SI analysis for high-speed nets: impedance, reflection, crosstalk, TDR, timing, transient.
• Collaborate with schematic/layout/mechanical teams to ensure SI/PI/EMC compliance.

Responsibilities

• Perform SI/PI/EMI simulations and validate results.
• Provide design recommendations based on simulation outcomes.
• Review PCB design constraints with cross-functional teams to ensure compliance.

Skills

Crosstalk Analysis

TDR Analysis

S-parameters

DDR analysis

Eye diagram

Timing margin analysis

Tools

ANSYS HFSS 3D

SI-wave

Job description

Role & responsibilities

Experience in Package Level Signal integrity simulation and Power Integrity Analysis.

Must have knowledge ANSYS HFSS 3D and SI-wave for PI/SI/EMI simulations and validation, and provide design recommendations based on simulation results

Must done Signal Integrity (SI) analysis for high-speed and critical nets, including impedance control, reflection analysis, crosstalk (NEXT/FEXT), TDR, timing, and transient simulations.

Collaboration with schematic, layout, and mechanical teams to review PCB design constraints and ensure SI/PI/EMC compliance with locomotive and industrial standards

Preferred candidate profile

• Crosstalk Analysis ( Near-Field and Far-Field )
• Conducted analysis on Time Domain Reflectometry.
• Knowledge in S Y Z parameter along with RL, IL, Crosstalk
• Conduct DDR analysis in compliance with JEDED standards, including eye diagram and eye mask
• Evaluations to assess SI and timing margins for high-speed memory interfaces Designed and
• Generate Eye diagram masks for bus topology