Senior Technical Lead - CPU Physical Design

Intel Corporation; Bengaluru; Hybrid; INR 3,500,000 - 5,500,000; Full time

Job summary

Intel Corporation is seeking a Senior Technical Lead - CPU Physical Design to guide the physical implementation of next-generation CPU IPs from floorplanning to signoff. You will drive PPA optimization, design convergence, and methodology adoption across multiple projects, collaborating with Architecture, RTL, CAD, DFT, and Signoff teams.

The ideal candidate has 14+ years in ASIC/CPU physical design, strong leadership, and hands-on experience with industry tools and scripting to automate

Qualifications

• M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, VLSI, or related.
• 14+ years of industry experience in ASIC or CPU Physical Design.
• Strong expertise in floorplanning, placement, clock tree synthesis, routing, physical verification, STA, PI, and EM/IR.
• Hands-on with Synopsys Fusion Compiler, ICC2, Cadence Innovus, PrimeTime, StarRC, Calibre.
• Strong scripting and automation using Python, Tcl, Shell.

Responsibilities

• Lead physical design execution for CPU IPs from design planning through signoff.
• Provide technical leadership for floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Drive PPA convergence to meet aggressive frequency, power, and area targets.
• Collaborate with Architecture, RTL, CAD, DFT, Power, and Signoff teams to ensure successful implementation.
• Mentor engineers and drive CAD methodology improvements and automation.

Job description

## Job Description:We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The successful candidate will provide technical leadership across the physical design lifecycle, driving PPA optimization, execution excellence, methodology adoption, and design convergence for high-performance CPU products.The ideal candidate brings deep expertise in advanced-node physical design, strong technical leadership, and a proven track record of delivering complex CPU, SoC, or high-performance IP designs.Key ResponsibilitiesLead physical design execution for CPU IPs from design planning through signoff.Provide technical leadership for:Floorplanning and Design PlanningPlacement and OptimizationClock Tree SynthesisRouting and Physical VerificationTiming ClosurePower and Area OptimizationSignoff ReadinessDrive PPA convergence and deliver aggressive frequency, power, and area targets.Define and execute physical design strategies for advanced CPU architectures and technology nodes.Partner closely with Architecture, RTL, Circuit Design, DFT, CAD, Power, and Signoff teams to drive implementation success.Lead resolution of complex implementation, timing, congestion, and power challenges.Drive methodology improvements and adoption of best practices across multiple projects.Evaluate implementation tradeoffs and provide technical recommendations that influence architecture and design decisions.Mentor and guide engineers across the physical design organization.Collaborate with CAD teams to improve efficiency through automation, methodology enhancements, and AI-driven workflows.Support planning, estimation, risk assessment, and execution tracking for physical design deliverables.Contribute to hiring, technical interviews, and development of engineering talent.## **Qualifications:**Minimum QualificationsM.Tech/MS/PhD in Electrical Engineering, Computer Engineering, VLSI, or a related discipline.14+ years of industry experience in ASIC or CPU Physical Design.Proven experience delivering successful products through complete physical implementation and signoff cycles.Strong expertise in:Floorplanning and Design PlanningPlacement and OptimizationClock Tree SynthesisRouting and ClosureStatic Timing AnalysisSignal IntegrityPower Integrity and EM/IRPhysical VerificationHands-on experience with industry-standard implementation tools such as:Synopsys Fusion CompilerICC2Cadence InnovusPrimeTimeStarRCRedHawkCalibreStrong scripting and automation experience using:PythonTclShellPreferred QualificationsExperience delivering high-performance CPU core, cache, fabric, or compute IP designs.Experience with advanced process technologies such as Intel 18A/14A, TSMC N3/N2, or equivalent.Deep understanding of:Physical design methodologiesAdvanced timing closure techniquesHierarchical implementationVariation-aware design methodologiesPower-aware implementationExperience leading geographically distributed teams.Experience driving CAD methodology improvements and automation initiatives.Familiarity with AI, Machine Learning, and Agentic AI applications for design automation and productivity enhancement.## Job Type:Experienced Hire## Shift:Shift 1 (India)## Primary Location:India, Bangalore## Additional Locations:## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \\* Job posting details (such as work model, location or time type) are subject to change.