Senior Staff Engineer, Chip Implementation

Renesas Electronics; India; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Renesas Electronics is seeking a Senior Staff Engineer in India to drive chiplet-based MCU implementation. You will lead RTL-to-gate synthesis, perform STA and timing closure across multiple modes, and collaborate across RTL, DFT, physical design, and architecture teams to ensure power, performance, and area targets are met.

The role emphasizes cost-sensitive, low-power MCU design on mature nodes, with strong scripting skills (Tcl/Perl/Python) to automate flows and improve efficiency.

Qualifications

• BTech/MTech in Electrical/Electronic Engineering, Computer Engineering, or Computer Science with 10+ years of ASIC/SoC implementation experience.
• Significant contribution to synthesis and timing closure for complex SoC designs.

Responsibilities

• Support RTL-to-gate synthesis for complex chiplet-based and multi-die MCU designs using industry-standard tools.
• Contribute to timing, power, and area optimization while meeting mature-node design constraints.
• Help drive static timing analysis and timing closure across multiple modes, corners, and operating conditions.
• Provide strong technical support to resolve implementation issues with RTL, DFT, physical design, verification, architecture, and package teams.
• Contribute to full-chip constraints and design optimization strategies for convergence.
• Execute and improve synthesis, STA, ECO and timing closure methodologies for cost-sensitive, low-power MCU designs.
• Evaluate EDA tools, flows, automation opportunities, and methodology improvements.

Skills

Synthesis

STA

Timing closure

UPF/CPF power intent

Power optimization

Multi-die design

Chiplet interfaces (SPI, I2C, Ethernet

Scripting (Tcl, Perl, Python)

ECO flows

RTL-to-gate flow

Education

BTech/MTech in Electrical/Electronic Engineering, Computer Engineering, or Computer Science

Tools

Synopsys Cadence synthesis tools

STA tools

Implementation sign-off flows

Job description

Job Description

We are seeking aSenior StaffEngineer, ChipImplementationtohelp drivesynthesis, static timing analysis,and timing closurefor low-power, chiplet-based MCU designs implemented on cost-optimized mature process nodes.This rolewill work closely with the overall chip implementation lead and contribute todesign convergence,methodology execution,technicalissue resolution, anddelivery against power, performance, area, quality, and schedule targets.

• Support and helpdriveRTL-to-gate synthesis for complexchiplet-based andmulti-dieMCUdesignsusing industry-standardimplementationtools, under the guidance of the overall implementation lead

• Contribute totiming, power, and areaoptimizationwhilemeetingmature-nodedesignconstraintsand product cost targets

• Help drivestatic timing analysisand timing closureacross multiplemodes,corners,andoperating conditions,supportingsign-off compliance for timing, power, and signal integrity

• Providestrongtechnicalsupportto resolve complex implementation and timing issues in collaboration with RTL, DFT, physical design, verification, architecture, and package teams

• Contribute tofull-chip constraints, block-to-top constraint alignment, and design optimization strategies required to achieve implementation convergence

• Executeandhelpimprovesynthesis, STA, ECO,and timing closure methodologies tailored for cost-sensitive, low-powerMCU designs

• Evaluate EDA tools, flows, automation opportunities, and methodology improvements to improve quality of results, efficiency, and turnaround time

Qualifications

• BTech/MTech in Electrical/Electronic Engineering, Computer Engineering, or Computer Science with10+ years of experience in ASIC/SoC implementation, includingsignificant contribution tosynthesis and timing closure for complex SoC designs

• Extensive hands-onexperiencewithmature-node technologiessuch as22nmor12nm,low-power designtechniques,and multi-clock domain designs

• Deep expertise withSynopsys/Cadencesynthesis tools,STA tools, and implementation sign-off flows

• Strong expertise inmulti-mode, multi-corner timing analysis,constraintdevelopment, constraint validation, and timing convergence

• Proven experience drivingtiming closureforexternal interfacessuch asSPI,I2C,Ethernet,CAN, and other SoC-level interfaces

• Strong experiencesupportinghierarchical timing closure, block-to-top constraint alignment, and full-chip timing convergence

• Expertisewith UPF/CPF-based power intent,low-power optimization,clock gating,multi-voltage domains, and power-aware implementation flows

• Strong experienceexecutingECO flows for timing fixes, power optimization,and late-stage design changes

• Strongscriptingand automationskillsinTcl, Perl,orPythonto improvesynthesis,STA, reporting, and regression efficiency

• Experience withtiming sign-off for chiplet-basedor multi-diedesigns isstrongly preferred

• Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus

• Can – do attitude,openness to new environment, people and culture

• Ability tocontribute totechnical problem solving,root-cause analysis, androbust implementation solutions for complex design challenges

• Ability towork effectively under theguidanceof the implementation leadand collaboratewith global cross-functional teams across RTL, DFT, physical design, verification, and architecture

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.