Senior Staff Engineer

Lattice Semiconductor; Pune District; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Lattice Semiconductor in Pune is seeking a Senior Staff Engineer to join a dynamic team. You will lead FPGA debug engine development, architect FPGA debug IP, and guide UI integration, while mentoring junior RTL & UI engineers for high-quality implementations.

The role emphasizes collaboration with marketing, QA, and engineering to deliver robust FPGA tooling and scalable design methodologies in a fast-paced, global environment.

Qualifications

• Masters in Electrical engineering/Computer engineering or related field.
• Strong communication skills.
• Expertise in HDL languages (Verilog/System-Verilog and VHDL).
• Expertise hardware design experience.
• Experience with FPGA design and debugging methodologies.
• Proficiency in synthesis tools.
• Proficiency in simulation tools from leading EDA vendors.
• Proficiency in testbench/test-vector creation.
• Proficiency in C/C++, TCL, Python.
• Proficiency in protocols such as Serdes, Ethernet, PCIe or DDR.

Responsibilities

• Lead the design and development of FPGA debug engine in Lattice EDA suite.
• Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features.
• As a principal RTL Engineer, work with marketing to generate architecture and specifications for new FPGA debug IP and guide QA.
• Mentor and guide junior RTL & UI engineers working on FPGA debug IP.
• Maintain high standards of architecture, implementation quality, performance, and reliability.
• Improve development methodologies and processes.

Skills

RTL System Design

FPGA design

HDL: Verilog/SystemVerilog/VHDL

C/C++

Python/TCL

Education

Masters in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

Simulation tools (EDA)

Testbench creation

Job description

Lattice Overview There is energy hereenergy you can feel crackling at any of our international locations. Its an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what youre looking for.

Responsibilities & Skills

Lattice Semiconductor is seeking a Senior Staff Engineer to join team in Pune. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.

Accountabilities:

• Lead the design and development of FPGA debug engine in Lattice EDA suite.
• Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features.
• As a principal RTL Engineer, you will work closely with marketing requirements and generate functional architecture and specifications for new FPGA debug IP functionality and guide the QA teams and ensure that implementations match design intent.
• Mentor and guide junior RTL & UI engineers working on FPGA debug IP, fostering a culture of continuous improvement and innovation.
• Maintain high standards of architecture, implementation quality, performance, and reliability.
• Improve development methodologies and processes.

Qualifications

• Masters in Electrical engineering/Computer engineering or related field with experience in RTL System Design and EDA experience.
• Strong communication skills.
• Expertise in HDL languages (Verilog/System-Verilog and VHDL).
• Expertise hardware design experience.
• Experience of Hardware Design experience using FPGAs.
• Experience on FPGA debugging methodologies.
• Proficiency in synthesis tools.
• Proficiency in simulation tools from leading EDA vendors.
• Proficiency in testbench/test-vector creation.Proficiency in C/C++ , TCL, Python languages.
• Proficiency in protocols such as Serdes interface, Ethernet, PCIe or Memory DDR is required.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com.

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At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.

Applications are welcome from all qualified candidates.

Lattice

Feel the energy. .