Senior Staff Design Verification Engineer

GlobalFoundries inc.; India; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

GlobalFoundries inc. in India is hiring a Senior Staff Design Verification Engineer to lead advanced verification for complex SoC and subsystems.

You will design and maintain UVM-based environments, drive verification planning, and collaborate with architecture, RTL, and design teams to ensure silicon quality and timely product delivery. The role emphasizes constrained-random testing, coverage models, and debugging across block and full-chip levels.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering or related; 8+ years in DV/SoC verification.
• Strong expertise in SystemVerilog and UVM-based verification.
• Proven experience building complex verification environments for subsystem and full-chip verification.
• Hands-on constrained-random verification, assertions (SVA), coverage-driven verification, and debugging.
• Experience with processors, memory subsystems, interconnects, and complex SoC architectures.
• Proficiency in scripting languages such as Python, Perl, Tcl, or Shell for automation.
• Excellent analytical, problem-solving, and communication skills.
• Ability to work effectively in a global, multicultural engineering environment; travel up to 10%.

Responsibilities

• Develop and maintain advanced UVM-based verification environments for complex SoC and subsystem designs.
• Define verification plans based on architecture and design specifications.
• Create reusable verification infrastructure, agents, scoreboards, monitors, and checkers to support multiple projects.
• Develop constrained-random and directed test scenarios to validate functionality and corner-case behavior.
• Verify processor, memory subsystems, interconnects, sensor, and peripheral subsystems at both block and SoC levels.
• Design and implement stimulus generation, protocol checkers, assertions, and coverage models.
• Analyze code coverage, functional coverage, and assertion coverage to ensure verification completeness.
• Debug RTL, testbench, integration, and simulation failures and drive resolution with cross-functional design teams.
• Enhance regression automation, reporting frameworks, and verification productivity methodologies.
• Promote reuse of verification components and best practices across programs and future product developments.
• Mentor junior verification engineers and contribute to verification methodology improvements across the organization.

Skills

SystemVerilog

UVM-based verification

Constrained-random verification

Assertions (SVA)

Coverage-driven verification

Debugging

Python scripting

Education

Bachelor's degree in Electrical Engineering / Electronics Engineering / Computer Engineering / VLSI

Master's degree in Electrical Engineering / Electronics Engineering / Computer Engineering

Job description

**Senior Staff Design Verification Engineer** **About GF**GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power-efficient and high-performance solutions for high-growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted technology partner for customers around the world. GF's talented global team remains focused every day on security, longevity, and sustainability. For more information, visit www.gf.com. **Introduction**The Senior Staff Design Verification Engineer is a senior technical contributor within the Smart Analog and Sensors responsible for delivering high-quality verification solutions for complex System-on-Chip (SoC) products. This role drives verification planning, methodology development, testbench architecture, functional validation, coverage closure, and debug activities across multiple subsystems and full-chip designs. The engineer will collaborate closely with architecture, RTL, design, and system teams to ensure robust silicon quality and successful product execution. **Your Job*** Develop and maintain advanced UVM-based verification environments for complex SoC and subsystem-level designs.* Define comprehensive verification plans based on architecture and design specifications.* Create reusable verification infrastructure, agents, scoreboards, monitors, and checkers to support multiple projects.* Develop constrained-random and directed test scenarios to validate functionality and corner-case behavior.* Verify processor, memory, interconnect, sensor, and peripheral subsystems at both block and SoC levels.* Design and implement stimulu* s generation, protocol checkers, assertions, and coverage models.* Analyze code coverage, functional coverage, and assertion coverage to ensure verification completeness.* Debug RTL, testbench, integration, and simulation failures and drive resolution with cross-functional design teams.* Enhance regression automation, reporting frameworks, and verification productivity methodologies.* Promote reuse of verification components and best practices across programs and future product developments.* Mentor junior verification engineers and contribute to verification methodology improvements across the organization. **Other Responsibilities*** Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.* Support continuous improvement initiatives and engineering excellence across verification flows and methodologies.* Collaborate effectively within global cross-functional teams to achieve project milestones and product quality goals.**Required Qualifications*** Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, or related discipline.* Minimum 8 years of industry experience in digital design verification or SoC verification.* Strong expertise in SystemVerilog and UVM-based verification methodologies.* Proven experience developing complex verification environments for subsystem and full-chip verification.* Hands-on experience with constrained-random verification, assertions (SVA), coverage-driven verification, and debugging.* Experience verifying processors, memory subsystems, interconnects, and complex SoC architectures.* Strong understanding of RTL design concepts and simulation/debug methodologies.* Experience with industry-standard simulators and verification tools.* Proficiency in scripting languages such as Python, Perl, Tcl, or Shell for automation.* Excellent analytical, problem-solving, and communication skills.* Ability to work effectively in a global, multicultural engineering environment.* Travel: Up to 10% as required for project collaboration. **Preferred Qualifications*** Master's degree or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.* Experience in automotive, radar, sensor, mixed-signal, or safety-critical semiconductor products.* Knowledge of formal verification techniques and low-power verification methodologies.* Experience with emulation, FPGA prototyping, or hardware/software co-verification.* Familiarity with ARM-based SoC architectures and industry-standard bus protocols such as AXI, AHB, APB, PCIe, or Ethernet.* Experience in verification automation frameworks, CI/CD integration, and regression infrastructure.* Demonstrated technical leadership and mentoring experience.