Senior SoC Design Verification Engineer

quadric technologies; Pune District; On-site; INR 4,000,000 - 6,000,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Equity with the business

Paid Parental Leave

PF Retirement Plan

Flexible PTO

Winter holiday shutdown

Catered lunch daily

Downtown Pune office

Job summary

Quadric is seeking a Senior SoC Design Verification Engineer in Pune to lead verification for GPNPU-based SoCs. You will design and implement verification environments, drive verification using directed and random stimuli, and coordinate with HW and SW teams to ensure full coverage and robust tapeout readiness.

You will collaborate on testbench architecture, leverage VIPs, Verilog/C Co-Simulation, and Python scripts to validate complex subsystems, NoC/PCIe/UCIe, and DDR, while reporting progress

Qualifications

• 5+ years of design verification on complex SoC/ASICs.
• Deep expertise in UVM and SoC verification practices.
• Proficiency in SystemVerilog/Verilog, assembly, and Python.
• Hands-on verification of NoC/PCIe/UCIe/DDR IP.
• Strong computer architecture background with VCS and co-simulation.

Responsibilities

• Architect and build scratch-built testbenches for SoC verification.
• Document verification test plans with architects, HW and SW teams.
• Implement scalable testbenches using VIPs and internal utilities.
• Develop directed and random drivers, plus assembly/C++ programs to stress-test subsystems.
• Verify SoC subsystems and 3rd-party IP (NoC, PCIe/UCIe, DDR).
• Leverage VCS, Verilog/C Co-Simulation and Python to run test suites.
• Track and report verification progress using coverage metrics.

Skills

UVM methodology

SoC verification

SystemVerilog/Verilog

assembly programming

Python scripting

3rd-party IP verification

VCS

computer architecture

Tools

VCS

Job description

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

The Opportunity

Quadric is building a revolutionary new processor-based SoC architecture. As a Senior SoC Design Verification Engineer, you will join the ground floor of our chip design team, taking technical leadership in architecting and building our SoC-level verification environment from scratch. You will collaborate closely with architects, hardware engineers, and software teams to ensure high quality and complete verification coverage for our next-generation GPNPU-based SoCs.

What You'll Do

Testbench Architecture & Test Plan Development

• Architect and build novel, scratch-built testbenches for SoC-level verification of our GPNPU-based SoCs.

• Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans.

• Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.

Test Execution & Verification Coverage

• Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration.

• Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).

• Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites.

• Track, analyze, and communicate verification progress across teams using functional and code coverage metrics.

What Success Looks Like

Within your first 6–12 months, you'll:

• Build out and deploy a fully functional, scratch-built SoC-level UVM verification environment.

• Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks.

• Establish robust co-simulation pipelines that validate HW/SW execution before tapeout.

What We're Looking For

Required

• Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs.

• Deep expertise in UVM methodology and leading SoC-level verification practices.

• Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.

• Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).

• Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation.

What We Offer

In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our India-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:

• Medical, dental, and vision insurance

• Equity with the business

• Paid Parental Leave

• PF Retirement Plan

• Flexible PTO

• Winter holiday shutdown

• Catered lunch each day in our office

• Downtown Pune office location, close to shops, cafes, and local amenities

• Collaborative, low-ego culture with significant ownership and impact

• A work culture focused on innovative disruption

Equal Employment Opportunity

Quadric is an equal opportunity employer. We do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, sexual orientation, gender identity, marital status, medical condition, or any other characteristic protected by applicable federal, state, or local law

E-Verify and Right to Work Notices

Quadric participates in the E-Verify program to confirm employment eligibility for U.S.-based roles. As part of this process, applicants may review the following notices, which explain your rights and our participation in E-Verify. These notices are provided in English and Spanish.

• E-Verify Participation Notice (English | Spanish)

• Right to Work Notice (English | Spanish)

No action is required from candidates during the application process. These notices are provided for informational purposes only.

Privacy

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