Senior Principal Software Engineer

Cadence Design Systems India Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Cadence Design Systems India Pvt Ltd in Bengaluru invites a Sr Principal Software Engineer to join our RTL-focused development team. You will work on advanced EDA software, mentor colleagues, and tackle challenging timing, area, and power constraints in synthesis.

The role requires deep RTL expertise in VHDL/Verilog, proficiency with Xcelium for simulations, and familiarity with DFT/MBIST. This is a research-driven environment with strong growth opportunities and mentorship.

Qualifications

• Hands-on RTL coding in VHDL or Verilog and system design.
• Run functional simulations with Xcelium; perform static timing analysis and DFT/MBIST familiarity.

Responsibilities

• R&D support for product engineers; diagnose and fix complex issues in synthesis results.
• Develop new features to improve timing, area, and power; mentor junior engineers.

Skills

RTL Coding

VHDL

Verilog

Xcelium

Scan/Timing Analysis

Education

BE/BTech/ME/MTech - Computer Science or related

Tools

Xcelium

Job description

Sr Principal Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Position: Sr. Principal Software Engineer
• Grade: T5
• Experience: 12- 16 Years
• Location: Bangalore/Noida

Job Responsibilities:

R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills.

Job Qualifications:

• BE/BTech/ME/MTech- Computer Science or others
• Required Skills The candidate should have hands‑on experience in RTL Coding. The candidate should be able to write, update, and optimize register-transfer level code using System Design Guide standards in VHDL or Verilog. run functional simulations (using Xcelium), static timing analysis, and design-for-test checks to find bugs. validate, test, and investigate performance/accuracy issues in the simulator. Knowledge of Design-For-Test (DFT) and/or Memory-Built-In-Self-Test (MBIST) is a plus.

Experience Level Senior Level