Senior Principal SoC Design Engineer — PCIe/CXL

Kandou AI; Bengaluru; Hybrid; INR 3,000,000 - 6,000,000; Full time

Job summary

Kandou AI is seeking a senior RTL design engineer to own PCIe/CXL subsystem RTL, from architecture through sign-off. You will collaborate with cross‑functional teams across global sites to ensure high‑performance, low‑latency data paths. The role demands deep expertise in SystemVerilog, PCIe/CXL, and ARM/AMBA integration.

The position offers a hybrid work model with global engineering collaboration and a pathway to leadership within the PCIe/CXL domain.

Qualifications

• Master's or Bachelor's degree in Electronics/Electrical Engineering (or equivalent).
• 18+ years of RTL design experience.
• End-to-end PCIe/CXL RTL design execution and sign-off.
• Strong hands-on SystemVerilog/Verilog RTL development.
• Expertise in PCIe protocol architecture, including link, transaction, and PHY interactions.

Responsibilities

• Own and drive PCIe/CXL subsystem RTL design definition, RTL implementation, and integration.
• Collaborate with Architecture teams to translate requirements into RTL designs.
• Work with Design Verification teams on test-plan reviews, debug, and coverage closure.
• Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Drive design quality improvements and reuse across projects.
• Mentor junior designers and provide technical leadership within PCIe/CXL domain.

Skills

SystemVerilog

RTL design

PCIe protocol

CXL architecture

ARM-based SoC integration

AMBA AXI/CHI/ACE

EDA tools

Scripting (Python/ Tcl/ Perl)

Version control (Git/SVN)

Debugging

Education

Electronics/Electrical Engineering

Tools

Synopsys EDA

Cadence EDA

Mentor/Siemens EDA

Job description

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

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About Kandou AI

Kandou AI is powering the future of AI infrastructure, operating at the intersection of information theory and semiconductor design. Kandou pioneered Copper MIMO (Chord Signaling) technology, transforming crosstalk and noise inherent in copper links into a mechanism that unlocks higher bandwidth, lower power, and greater scale for GPU, memory, network, and rack-scale connectivity. The company's product portfolio includes the Matterhorn USB4 Retimer, Regli PCIe Retimer, Zetti PCIe Switch, and Glasswing Chiplet Interconnect IP, and it is building next-generation AI systems spanning AI inference, CXL memory platforms, and ultra-high-speed scale-up/scale-out networking.

Headquartered in Lausanne, Switzerland, Kandou AI has a global engineering footprint including design centers in the United States, United Kingdom, Germany, Taiwan, and a newly established India Chip Design Headquarters in Hyderabad, reflecting continued investment in world-class semiconductor design talent. Kandou fosters a hybrid, flexible working culture built around autonomy, teamwork, and a shared commitment to pushing the boundaries of connectivity technology.

Responsibility and Authority

No.

Description

1

Own and drive PCIe/CXL subsystem micro-architecture definition, RTL implementation, and integration.

2

Collaborate closely with Architecture teams to translate requirements into robust RTL designs.

3

Work with Design Verification teams on test-plan reviews, debug, and coverage closure.

4

Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.

5

Support silicon bring-up and post-silicon debug, working with firmware and validation teams.

6

Drive design quality improvements, coding best practices, and reuse across projects.

7

Participate in design reviews, milestone reviews, and cross-functional technical discussions.

8

Mentor junior designers and provide technical leadership within the PCIe/CXL design domain.

9

Individual responsibilities for this role are defined by Kandou's executive team on a project-by-project basis and may vary from this job description.

No.

Description

1

Master's or Bachelor's degree in Electronics/Electrical Engineering (or equivalent), with 18+ years of relevant experience in RTL design.

No.

Description

1

End-to-end PCIe/CXL subsystem RTL design execution and sign-off.

2

Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure.

3

Strong hands‑on experience in SystemVerilog / Verilog RTL development.

4

Expertise in PCIe protocol architecture, including link, transaction, and PHY interaction layers.

5

Strong understanding of CXL.io, CXL.cache, and CXL.mem architectures.

6

Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).

7

Experience designing high‑performance, low‑latency data paths and handling ordering, coherency, and error mechanisms.

8

Solid grasp of clocking, resets, CDC/RDC, low‑power techniques, and performance optimization.

9

Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows.

No.

Description

1

Proficient in debugging functional and performance issues at subsystem and SoC levels.

2

Experience using industry‑standard EDA tools from Synopsys, Cadence, and Mentor/Siemens.

3

Proficient in scripting languages such as Tcl, Perl, or Python.

4

Experience with version control systems such as Git, SVN, etc.

5

Strong communication and presentation skills, comfortable interfacing across cross‑functional and geographically distributed engineering teams.