Senior Principal Physical Design Engineer

Astera Labs; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Astera Labs is seeking a Senior Principal Physical Design Engineer in Bengaluru to lead back-end SoC efforts from architecture to GDSII. You will drive synthesis, place-and-route, timing closure, and DFT using Cadence/Synopsys flows for 16nm or smaller nodes.

The ideal candidate has 6+ years in server/storage/networking SoCs, strong Python/Perl scripting, and proven ownership of multi-block or full-chip designs, working with IP vendors and RTL/hard-mac blocks.

Qualifications

• Hands-on knowledge of synthesis, place & route, CTS, extraction timing analysis/STA and backend tools for 16nm or smaller (preferably 7nm).
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at block and full-chip level.
• Ownership from architecture to GDSII for full-chip or multi-block designs.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiar with SystemVerilog/Verilog and DFT techniques.
• Experience collaborating with IP vendors for RTL and hard-mac blocks.
• Scripting skills in Python or Perl.

Skills

Synthesis & timing analysis

Timing closure & formal verification

Architecture to GDSII ownership

Cadence/Synopsys PD tools

SystemVerilog/Verilog

DFT tools & techniques

IP vendor collaboration (RTL & hard-m

Python/Perl scripting

Education

Bachelor's in EE/Computer

Master's degree preferred

Tools

Cadence

Synopsys

Job description

Senior Principal Physical Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com .

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
• ≥6 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required experience:

• Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Experience with DFT tools and techniques.
• Experience in working with IP vendors for both RTL and hard-mac blocks.
• Good scripting skills in python or Perl

Preferred :

• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
• Familiarity with DFT test coverage and debug.
• Familiarity with ECO methodologies and tools.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.