Senior Physical Design Architect

Eximietas Design; Hyderabad; On-site; INR 14,327,000 - 22,923,000; Full time

Job summary

Eximietas is hiring Senior Physical Design Engineers, Leads and Architects to work on PD CAD, PD Power, Physical Verification and PD EMIR across advanced nodes.

Locations include San Jose (Bay Area) and Austin, USA with eligibility for USA permanent residents. The role requires 6+ years in Physical Design and hands-on experience with 10nm/7nm/5nm nodes.

You'll develop and optimize flows, mentor teams, and deliver robust P&R solutions for challenging customer designs.

Qualifications

• Minimum 6 years of experience in Physical Design with mainstream P&R tools.
• Experience on 10nm / 7nm / 5nm and below technology node designs.
• Develop and optimize flows for placement, CTS, and routing.
• Solve critical customer design challenges across performance, power, and area.
• Provide training, deployment support, and technical guidance to customers.

Responsibilities

• Lead and mentor teams on PD CAD, PD Power, and Physical Verification.
• Collaborate with RTL/implementation teams on Synthesis and timing.
• Drive floorplanning and macro placement for advanced nodes.

Skills

Place & route flows

Low-power design

Synthesis

Floorplanning

STA & sign-off

Physical Verification

Education

Bachelor's/Master's in Electronics/EE/VLSI

Tools

P&R tools

Synthesis tools

Job description

Eximietas is Hiring – Senior Physical Design Engineers, Leads & Architects.

Experience: 6 to 20+ Years

PD CAD

PD Power

Physical Verification

PD EMIR

Locations:

• San Jose (Bay Area), USA
• Austin, USA
• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Qualifications:

• Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI Engineering
• Minimum 6 years of experience in Physical Design with mainstream P&R tools
• Work on 10nm / 7nm / 5nm and below technology node designs
• Solve critical customer design challenges across performance, power, and area
• Develop and optimize flows/methodologies for placement, CTS, and routing
• Provide training, deployment support, and technical guidance to customers

Required Technical & Professional Expertise:

• Strong experience in place & route flows (placement, CTS, routing, timing optimization)
• Knowledge of hierarchical designs and/or low-power implementation
• Experience in Synthesis and collaboration with RTL/implementation teams
• Expertise in Floorplanning (macro placement, padring, power grid, custom analog routing)
• Strong understanding of STA, constraints, parasitic extraction & sign-off
• Awareness of Physical Verification (DRC/LVS/DFM, chip finishing)

Interested candidates, please share your resumes: [e-mail]

Referrals are highly appreciated....! please feel free to forward this within your network...!

Best regards,

Associate VLSI Manager - Talent Acquisition | Visakhapatnam