Senior Manager Verification

Infineon Technologies AG; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Infineon Technologies AG in Bengaluru seeks a seasoned ASIC/SoC Verification Leader with 12+ years of functional verification experience. You will own the full-chip verification strategy, coverage closure, sign-off criteria, and DV execution while guiding high-performing verification teams across architecture, design, safety, DFT, and product groups to ensure production-ready silicon.

The role requires mastery of SystemVerilog/UVM, strong planning, multi-clock/CDC, formal methods, and testbench

Qualifications

• 12+ years in ASIC/SoC functional verification with leadership experience
• 3+ years leading a DV team or owning full-chip verification sign-off
• Tape-out, silicon bring-up and production release accountability
• Multiphase power management and mixed-signal verification experience preferred
• ISO 26262 verification exposure is a plus

Responsibilities

• Own full-chip and subsystem verification strategy with clear coverage goals
• Define verification plans traceable to requirements and sign-off criteria
• Drive coverage closure and defensible exclusion rationale
• Oversee regression infrastructure, triage, and scale-wide turnaround
• Represent verification in cross-functional forums (design, safety, DFT, physical design, product)
• Own verification schedule, resources, risk, and reuse across variants
• Lead expert SystemVerilog/UVM efforts across multi-agent environments
• Advance formal verification, property checking, and DPI-based models
• Coordinate with architecture and product teams to ensure robust silicon

Education

Master’s degree in Electrical/Electronic Engineering

Bachelor’s degree or equivalent depth

Tools

SystemVerilog

UVM

DV/Verification planning

C/MATLAB golden models

Formal verification

Job description

We're looking for a seasoned ASIC/SoC Verification Leader with 12+ years of experience in functional verification and a proven track record of driving complex SoCs from verification planning through tape-out, silicon bring-up, and production release. In this role, you'll own the full-chip verification strategy , coverage closure, sign-off criteria, and DV execution while leading high-performing verification teams. You'll work across architecture, design, safety, DFT, and product teams to ensure robust, scalable, and production-ready silicon.

Responsibilities

Key responsibilities in your new role Verification leadership Own the full-chip and subsystem verification strategy: what is proven where, and why that partition is sufficient. Verification planning traceable to requirements, with defined coverage goals and explicit sign-off criteria. Coverage closure - functional and code coverage, and defensible exclusion rationale. Regression infrastructure, triage discipline and turnaround at scale. Represent verification in cross-functional forums - design, architecture, safety, DFT, physical design, product definition. Own verification schedule, resource and risk; elevate early with options. Drive methodology and reuse across subsystems and product variants. Expert System Verilog and UVM: multi-agent environments, virtual sequences, scoreboards, reuse across block, subsystem and chip level. Register/RAL verification and register-generation flows. Multi-clock and CDC-aware verification; reset and power-sequencing scenarios. Formal verification: property checking and sequential equivalence and knowing when formal beats simulation Reference-model-based verification, including C/MATLAB golden models integrated via DPI and bit-exact correlation for data paths. Mixed-signal verification Verification of the digital-analog boundary: control/status handshakes, trim and calibration load, start-up and POR sequencing.

Qualifications and Skills

Educational background Master’s degree in electrical/Electronic Engineering, Microelectronics. Bachelor’s with equivalent depth considered. Work experience 12+ years in ASIC/SoC functional verification, including 3+ years leading a DV team or owning full-chip verification sign-off. Multiphase power management controller experience is strongly preferred At least two SoCs verified through tape-out, silicon bring-up and production release, with accountability for the sign-off decision. Mixed-signal SoC verification is essential ISO 26262 verification, including fault-injection campaigns and diagnostic coverage evidence is a plus Soft Skills Independent judgement - able to say "not ready" under schedule pressure and make it stick. Systems thinking across chips and subsystem boundaries Precision in communication - states clearly what has and has not been proven Credible technical authority with senior engineers, while genuinely open to being challenged. Constructive relationship with design without losing independence. Mentoring and team building across time zones and cultures. Pragmatism - allocates priorities and effort by risk #WeAreIn for driving decarbonization and digitalization.

Company Culture and Diversity

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Vidhi Thakkar