Senior Manager - SoC Validation

Renesas Electronics; Hyderabad; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Renesas Electronics seeks a senior silicon validation leader to drive end-to-end validation activities across pre-silicon and post-silicon stages, including ATE test development. This role focuses on silicon quality, yield improvements, and production readiness through collaboration with Design, DV, DFT, Product Engineering, ATE, Applications, Firmware and Quality teams.

The candidate will lead silicon bring-up and debug of complex SoCs, develop validation plans and coverage strategies, and

Qualifications

• 18+ years in SoC validation, characterization, product engineering, or ATE domains.
• Experience across complete silicon lifecycle: wafer probe, package test, final test, system validation.
• Strong skills in validation planning, test specification, and coverage strategy.

Responsibilities

• Lead silicon bring-up and debug activities for complex SoCs.
• Own functional, subsystem, and system-level validation.
• Develop validation plans, test specifications, and coverage strategies.
• Drive customer use-case and scenario validation.
• Perform stress, reliability, concurrency, and corner-case validation.
• Define and execute silicon characterization plans across PVT corners.
• Characterize timing, performance, power, thermal, and analog parameters.
• Correlate silicon measurements against simulation models and specifications.
• Analyze silicon variation and identify design/process-related issues.
• Generate characterization reports for product release and datasheet validation.

Skills

SoC Validation

Characterization

ATE

Program Management

Vendor Management

Debugging

Test Coverage

Reliability Testing

Tools

DFT Tools

Wafer Probe Equipment

Job description

Lead and manage end-to-end silicon validation activities spanning pre-silicon correlation, post-silicon functional validation, system validation, bench characterization, wafer probe evaluation, and ATE test development. Drive silicon quality, yield improvement, characterization, and production readiness while collaborating with Design, DV, DFT, Product Engineering, ATE, Applications, Firmware, and Quality teams. This enhancement aligns with responsibilities reflected in internal validation and evaluation materials.

Key Responsibilities

• Lead silicon bring-up and debug activities for complex SoCs.
• Own functional, subsystem, and system-level validation.
• Develop validation plans, test specifications, and coverage strategies.
• Drive customer use-case and scenario validation.
• Perform stress, reliability, concurrency, and corner-case validation.
• Define and execute silicon characterization plans across PVT (Process, Voltage, Temperature) corners.
• Characterize timing, performance, power, thermal, and analog parameters.
• Correlate silicon measurements against simulation models and specifications.
• Analyze silicon variation and identify design/process-related issues.
• Generate characterization reports for product release and datasheet validation.

Wafer Probe / CP Evaluation

• Manage wafer-level electrical characterization and evaluation.
• Drive correlation between wafer probe, package test, and system validation results.
• Analyze yield excursions and process-related failures.
• Support DFT and Product Engineering teams in test coverage improvement.
• Develop screening methodologies and guard-band recommendations.

ATE Validation

• Collaborate with DFT and Product Engineering teams on ATE strategies.
• Review and optimize wafer sort and final test coverage.
• Validate production test programs and characterization limits.
• Drive ATE correlation with bench and system-level measurements.
• Support yield ramp, test time optimization, and cost reduction initiatives.

Leadership & Program Management

• Lead global validation teams and vendor resources.
• Manage schedules, resource planning, risk assessment, and execution.
• Mentor engineers in debug, characterization, and validation methodologies.
• Drive root-cause analysis and cross-functional issue resolution.

Qualifications

Required Skills & Experience

• 18+ years in SoC/System Validation, Characterization, Product Engineering, or ATE domains.
• Experience across the complete silicon lifecycle:
• Wafer Probe (CP)
• Package Test / Final Test
• System Validation
• Customer Support & Failure Analysis

SoC Validation Expertise

• SoC bring-up and silicon debug
• Functional and system validation
• Use-case and scenario validation
• Subsystem validation
• Stress and reliability testing
• Coverage planning and closure
• PVT characterization
• Timing and performance measurements
• Power and thermal characterization
• Analog and mixed-signal evaluation
• Correlation analysis

Wafer Probe & Product Engineering

• Yield analysis and yield improvement
• Parametric characterization
• Screening and guard-banding techniques
• Failure analysis flow

ATE Expertise

• Wafer sort and final test programs
• Test coverage analysis
• Correlation between ATE, Bench, and System results