Senior Lead Design Engineer

NXP Semiconductors NV; Bengaluru; Presencial; INR 3.500.000 - 6.500.000; Jornada completa

Descripción de la vacante

NXP Semiconductors Bengaluru is seeking an experienced ASIC design professional to drive SOC development from specification through tape-out. The role requires hands-on RTL coding, debug infrastructure, and deep familiarity with ARM Cortex-based SoCs.

You will collaborate with verification, DFT, Synthesis teams to ensure production-quality silicon, and own clocking, reset, and interconnect architectures across multiple cohorts and products.

Formación

• Experience in RTL design from specification to tape-out.
• Hands-on Verilog RTL coding and integration of debug logic.
• Exposure to Arm Cortex-M/A/R based SoC debug infrastructure.

Responsabilidades

• Leading SOC debug, micro-architecture, and integration from initial spec to tape-out.
• Drive and implement best SoC design methodologies across business lines.
• Sign-off RTL, timing constraints, CDC, RDC; work with verification, DFT, synthesis for production-quality silicon.
• Document SOC design and micro-architecture for cross-functional usage.
• Provide debug design support for silicon-related post-silicon issues.

Conocimientos

RTL design

Arm Cortex

CoreSight

ASIC design

Verilog RTL

Debug infrastructure

Clocking & Reset

Bus protocols (AXI/ACE/APB)

SOC integration

Trace32

RTL signoff tools

Herramientas

Trace32

RTL signoff tools

Descripción del empleo

NXP's MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Edge, Radar Processing and Advanced Analog business lines. MME's SoC Front End team produces design solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-cohort devices compliant with the latest automotive and industrial safety and security standards.

Scope Of Responsibilities/Expectations

• Leading SOC debug , micro-architecture, and integration of the System on Chip (SOC) from initial specification till tape out and beyond
• Drive and implement best SoC design methodology/practices and scale it across different business lines.
• Signing off RTL, timing constraints, CDC, RDC and work with different functions like verification, DFT, synthesis, etc. to get to a production quality Silicon.
• Documenting the SOC design and micro-architecture for usage by other SOC functions
• Provide debug design support for any silicon related debugs of chips in post-silicon phase.

Specific Knowledge/Skills

• ASIC designers with experiences in all aspects of RTL design flow from Specification/Micro-architecture definition to design.
• Experience with Arm Cortex-M/A/R processor-based SoC debug infrastructure handling
• ARM CoreSight, ETM, STM, DAP, CTI, JTAG, SWD, Trace32, ARM Debug, ARM Trace integration exposure
• Experience: 5-10 Years in IP/SOC design with successful delivery of production quality chips
• Good knowledge of Digital Design and hands-on experience with Verilog RTL coding/integration of debug logic
• Should have a firm understanding and hands-on experience on Chip Assembly, IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis.
• Familiarity with Computer architecture: knowledge of microprocessors (ARM, RISC-V), bus protocols preferred (AXI/ACE/APB/ATB). Knowledge on CPU architecture, Core-sight and peripherals like PCIe, USB, DDRs is highly desirable.
• Strong domain knowledge of Clocking, Reset, System modes, debug, interconnect, safety, security and other architectures Know-how of Serial Interfaces, Multimedia, External Bus Interfaces
• Self-motivated to drive issues to closure. Should be a team player and willing to work with cross functional teams on issues resolution.
• Excellent written and verbal communication skill.
• Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.

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