Senior IP Micro Architect -Sr Lead/Staff

Nutanix; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited seeks a Senior IP Micro-architect to lead architecture definition and microarchitecture for complex custom Infrastructure IPs. The role requires hands‑on RTL design in Verilog/SystemVerilog, plus mentoring engineers and guiding IP development from concept to production silicon.

Focus areas include memory subsystem IP, NoC and high‑speed interconnect fabrics, performance optimization, and scalable interconnect architectures for next‑gen SoCs.

Qualifications

• 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design.
• Experience delivering complex custom IPs from concept to production silicon.
• Strong background in infrastructure IPs, NoC, interconnect fabrics, memory subsystems, or high-speed interface IPs.
• Deep knowledge of computer/SoC architecture, digital design, performance modeling, and synchronization.

Responsibilities

• Drive architecture and microarchitecture definition of complex custom Infrastructure IPs.
• Develop detailed microarchitecture specifications including datapath, control logic, packet formats, flow control, and state machines.
• Lead RTL development and collaborate with verification, physical design, firmware, and SoC teams.
• Evaluate trade-offs across performance, power, area, scalability, latency, and complexity.
• Design high-performance interconnect, memory, and protocol-centric IP solutions.
• Drive design reviews and technical decisions across projects.
• Support verification planning, debug, emulation, FPGA validation, and silicon bring-up.
• Ensure RTL quality through lint, CDC/RDC, synthesis, and timing closure.

Skills

SoC/IP Architecture

RTL Design

Verilog/SystemVerilog

Performance Modeling

Debugging/Problem-Solving

Communication Skills

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree

PhD

Tools

Lint

CDC/RDC

Synthesis

Timing Closure

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

• Role Focus :Core Domains Architecture definition, microarchitecture development, custom protocol design, RTL implementation, performance optimization, and silicon delivery for complex Custom IPs.


• Core Domains: Infrastructure IP, NoC, PCIe, CXL, memory systems, cache coherency, UALink, ESUN, and AI scale-up interconnect fabrics.


• Job Summary : Hands-on technical leader capable of driving IP from concept through production silicon while mentoring engineers and influencing architecture decisions. We are seeking a highly motivated and experienced Senior IP Micro-architect to join our Custom IP Team focused on developing next-generation Infrastructure IPs, memory subsystem solutions, and scalable interconnect architectures for high-performance SoCs. The ideal candidate will possess deep expertise in architecture definition, microarchitecture development, protocol design, RTL implementation, and performance optimization for complex custom IPs. This role requires strong technical leadership, hands-on design expertise, and the ability to drive IP development from architectural concept through silicon realization.

Key Responsibilities:

• Drive architecture and microarchitecture definition of complex custom Infrastructure IPs.


• Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines.


• Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams.


• Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity.


• Design and develop high-performance interconnect, memory, and protocol-centric IP solutions.


• Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects.


• Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities.


• Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies.


• Mentor junior engineers and provide technical leadership within the IP development team.


• Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.

Required Qualifications:

• 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design.


• Proven experience defining and delivering complex custom IPs from concept through production silicon.


• Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs.


• Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures.


• Hands-on RTL design experience using Verilog/SystemVerilog.


• Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals.


• Strong debugging, analytical, and problem-solving skills.


• Excellent verbal and written communication skills.


• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.


• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.


• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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