Senior Engineer - IC Design (RTL AMS)

Silicon Labs; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs in Hyderabad seeks an RTL Design Engineer for Mixed-Signal IPs to develop and verify digital RTL blocks within mixed-signal subsystems for modern SoCs. You will collaborate with analog and digital teams to ensure low-power, robust IP delivery through rigorous verification and timing analysis.

The role requires proficiency in Verilog/SystemVerilog, experience with co-simulation tools, and scripting for automation.

Qualifications

• 3+ years of digital RTL design experience with mixed-signal IP exposure.
• Proficiency in Verilog/SystemVerilog and synthesis/verification flows (lint, CDC).
• Familiarity with analog/mixed-signal concepts and interfaces.
• Experience with mixed-signal co-simulation tools is a plus.
• Experience with digital communication protocols (SPI, I2C, AXI).
• Scripting for automation (Python, Perl, TCL).

Responsibilities

• Develop synthesizable RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.
• Collaborate with analog design engineers to define digital-analog interfaces and control logic.
• Verify IPs via behavioral modeling, simulation, and co-verification with analog components.
• Participate in design reviews, micro-architecture definition, and documentation of timing interfaces.
• Perform lint, CDC, RDC checks and synthesis readiness analyses.
• Work with verification engineers to define test plans and drive coverage closure.
• Integrate IPs into SoC top-level RTL and troubleshoot timing issues.
• Contribute to design methodology improvements and reuse strategies.

Skills

Verilog/SystemVerilog

Mixed-signal IP

Scripting (Python, TCL, Perl)

Cross-functional collaboration

Debugging and verification

Education

B.E./B.Tech or M.S./M.Tech in Electrical/Electronics/Computer Engineering

Tools

Cadence AMS Designer

Synopsys VCS AMS

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Role Overview

The RTL Design Engineer for Mixed-Signal IPs is responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems that combine analog and digital functionalities. This role requires a deep understanding of digital design principles, interface with analog/mixed-signal teams, and strong verification and integration skills to ensure high-quality, low-power, and functionally robust IP delivery. The engineer will work closely with system architects, analog designers, and SoC teams to enable seamless integration of mixed-signal IPs into complex SoCs.

Key Responsibilities

• Develop synthesizable, high-quality RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.
• Collaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols.
• Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.
• Participate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces.
• Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
• Collaborate with verification engineers to define test plans, drive coverage closure, and debug issues across digital and analog boundaries.
• Integrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing issues during full-chip validation.
• Contribute to continuous improvement of design methodologies, automation scripts, and reuse strategies for mixed-signal IP development.

Qualifications

• 3+ years of experience in digital RTL design with strong exposure to mixed-signal IP or subsystem development.
• Proficiency in Verilog/SystemVerilog and experience with synthesis and static verification flows (lint, CDC).
• Familiarity with analog/mixed-signal concepts such as signal sampling, clocking, calibration, and power management.
• Hands-on experience with mixed-signal co-simulation tools (Cadence AMS Designer, Synopsys VCS AMS, etc.) is a plus.
• Good understanding of digital communication protocols (SPI, I2C, APB, AXI).
• Exposure to scripting (Python, Perl, TCL) for automation and design flow enhancements.
• Experience working in cross-functional environments involving analog, verification, and SoC integration teams.

Education

• B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering.

Key Competencies

• Strong understanding of digital design and verification fundamentals.
• Ability to work effectively across analog and digital domains in a collaborative environment.x
• Excellent debugging, problem-solving, and analytical skills.
• Good communication and documentation abilities.
• Passion for quality, efficiency, and innovation in mixed-signal IP design.

Success Metrics

• Timely delivery of functionally correct and synthesis-ready RTL for mixed-signal IPs.
• High quality and robustness verified through simulation, lint, and CDC sign-off.
• Effective collaboration with analog and SoC teams ensuring smooth IP integration.
• Contributions to methodology and flow improvements enhancing team efficiency.

Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making"

Benefits & Perks

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Equity Rewards (RSUs)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.