Senior Engineer I - Physical Design

FHLB Des Moines; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Microchip Technology Inc. is seeking a skilled Physical Design Engineer to drive mixed-signal microcontroller and SOC designs, delivering next-generation solutions.

You will perform floorplanning, placement, clock-tree synthesis, and timing closure while ensuring power integrity and signoff. The role requires deep expertise in low-power flows, industry tools, and collaboration across global teams.

Qualifications

• Bachelor or Master degree in Electrical/Electronic Engineering.
• 5+ years hands-on experience in Physical Design and related technical areas.
• Proficient with place-and-route flows and low power physical design methodologies.
• Strong scripting (TCL, PERL, Shell) and HDL knowledge (Verilog/VHDL).

Responsibilities

• Conduct floorplan exploration and optimization for accurate die sizing.
• Perform power-domain floor planning and grid implementation.
• Execute placement, routing, timing optimization, and clock-tree synthesis.
• Lead physical verification (DRC/LVS) and signoff activities.
• Interface with IP teams and CAD vendors to resolve issues and tape out silicon.

Skills

TCL scripting

PERL scripting

Shell scripting

Verilog

VHDL

Education

Bachelor/Master in Electrical/Electronic Engineering

Tools

Innovus / Fusion Compiler

Calibre

Redhawk

Starrcxt

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

Microchip’s DSPIC Business Unit is seeking a skilled and experienced Physical Design Engineer to join our global DSPIC Physical Design team. In this role, you will be instrumental in driving the successful execution of microcontrollers and microcontroller-based SOC designs, delivering the next generation of hierarchical, low power, mixed signal microcontroller solutions.

Key Responsibilities:

Implement complex mixed signal, low power designs using state-of-the-art FLASH process technologies. Work independently and efficiently on assigned project responsibilities, from new design exploration through delivery of GDS (netlist to GDSII flow) and Metal-only ECO implementation. Provide Physical Design support for test chip shuttles, including development work associated with new concepts and flow. Develop and enhance Physical Design flow and methodology, including comprehensive documentation. Conduct power integrity and reliability analysis, ensuring robust sign-off for all designs.

Detailed Job function:

Conduct floorplan exploration and optimization for accurate die size estimation. Perform power domain and voltage area-based floor planning, including power grid planning and implementation. Execute placement and optimization with a focus on timing, area, and power efficiency. Manage clock tree synthesis, balancing, and debugging to ensure robust clock distribution. Drive post-route timing optimization and timing closure to meet design specifications. Perform timing and signal integrity analysis at both chip and block levels. Ability to lead chip and block level physical implementation activities. Develop and refine physical design flow and methodology for improved efficiency and quality. Conduct physical verification, including DRC (Design Rule Check) and LVS (Layout Versus Schematic). Ensure IR drop and electromigration (EM) signoff for reliable power delivery. Implement timing and metal-only ECOs (Engineering Change Orders) as needed. Interface with internal and external IP teams, as well as CAD vendors, to resolve technical issues. Collaborate closely with synthesis, DFT, and other cross-functional global teams to achieve timely tapeout and ensure first-pass working silicon.

Requirements/Qualifications:

Bachelor of Engineering in Electrical / Electronic Engineering or Master of Engineering in Electrical / Electronic Engineering or Equivalent Minimum of 5 years of hands‑on experience in Physical Design and related technical areas, demonstrating a strong track record of successful project execution. Advanced knowledge of place and route methodologies, as well as low power physical design flows and methodologies. Proficiency with industry-standard physical implementation and analysis tools such as Innovus or Fusion Compiler, Calibre, Redhawk, Starrcxt, or equivalent EDA tools. Strong scripting skills in TCL, PERL, and Shell, along with working knowledge of hardware description languages such as Verilog and VHDL. Excellent analytical and debugging abilities, with a proactive approach to identifying and resolving technical challenges. Independent, self‑motivated, and capable of managing responsibilities. Outstanding oral and written communication skills, with the ability to clearly convey technical concepts and collaborate effectively within a team. Familiarity with advanced nodes is desirable.

Travel Time: 0% - 25%