Senior Engineer HDD

Data Patterns (India) Ltd.; Chennai District; In loco; INR 1.200.000 - 1.800.000; Tempo pieno

Descrizione del lavoro

Data Patterns (India) Limited is seeking an experienced engineer for requirements generation and RTL design using VHDL/Verilog. The role emphasizes DO-254 lifecycle expertise and exposure to synthesis, timing analysis, and design constraints.

The candidate should be proficient in PCIe, SERDES, and FPGA architectures, with strong digital and signal processing capabilities. The work includes DO-254 lifecycle responsibilities and continuous improvement of test and simulation environments.

Competenze

• Proficiency in Verilog/VHDL and exposure to DO-254 lifecycle.
• Experience with FPGA architectures and high-speed interfaces.
• Knowledge of timing analysis, synthesis, and timing closure processes.

Mansioni

• Requirements Generation and RTL design using VHDL/Verilog.
• Maintain and improve test and simulation environments.
• Engage in DO-254 lifecycle activities and coordination with hardware teams.

Conoscenze

Verilog/VHDL

Timing closure

High-speed protocols

System-level debugging

Tcl scripting

Formazione

BE in Electronics/ECE/EE

Master's Degree

Bachelor of Engineering

Strumenti

Vivado

Quartus

Logic analyzers

Descrizione del lavoro

Group Company: Data Patterns (India) Limited

Position description: Requirements Generation, RTL design using VHDL, Good knowledge in DO-254 lifecycle. Good exposure to synthesis, timing analysis and design constraints, FPGA architecture: Vilinx/Altera, Exposure to PCIe, Arinc protocols etc., Continuously improve test and simulation environment.

Primary Responsibilities:

• Requirements Generation, RTL design using VHDL, Good knowledge in DO-254 lifecycle. Good exposure to synthesis, timing analysis and design constraints, FPGA architecture: Vilinx/Altera, Exposure to PCIe, Arinc protocols etc., Continuously improve test and simulation environment.

Position Specific Requirements

• Proficiency in Verilog/VHDL, experience with Vivado or Quartus, and expertise in timing closure and high-speed protocols.
• Good in Digital and analytical skill.
• Good in Signal processing

Position Specific Skills

• Proficiency in PCIe/Ethernet protocols and Multi-Gigabit Transceivers (SERDES).
• Worked in the areas like High speed interface like PCIe, DDR, JESD & Ethernet.
• Expertise in Static Timing Analysis (STA), floorplanning, and timing closure.
• Balancing architectural trade-offs between Area, Power, and Speed performance.
• System-level troubleshooting using Tcl scripting and logic analyzers.
• Expertise in RADAR Digital Signal Processing.
• Category: Bachelor's Degree, Master's Degree
  
• Field specialization: Electronics and communication engineering, Electrical and Electronics engineering, Electronics and instrumentation
  
• Degree: , , Bachelor of Engineering - BE
  
• Academic score: 60
• Institution tier: 1,2,3,4

Required work experience

• Industry: Defense & Space|Electrical & Electronic Manufacturing|Machinery|Computer & Network Security