Senior Design Verification Engineer, Google Cloud

Google Inc.; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

Equity grants

Discretionary benefits

Job summary

Google Inc. is hiring for a role focused on AI/ML hardware acceleration in Bengaluru. You will work on TPU technology that drives innovative AI/ML applications and be responsible for the full verification life cycle, ensuring performance and accuracy. Candidates should have a Bachelor's in Electrical Engineering and extensive experience in digital verification, especially using SystemVerilog.

This role involves collaborating with design teams, identifying verification scenarios, and creating robust verification environments. Join us to shape cutting-edge technology!

Qualifications

• 8 years of experience in verification using SystemVerilog or Specman/E.
• Experience in the Networking domain for subsystems such as FPGAs or ASICs.
• English proficiency is required.

Responsibilities

• Plan verification of digital design blocks.
• Identify coverage measures for stimulus and corner-cases.
• Debug tests with design engineers.

Skills

SystemVerilog

Artificial Intelligence/Machine Learning

Problem-solving

Communication skills

Debugging

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in relevant field

Tools

Universal Verification Methodology (UVM)

Industry-standard simulators

Job description

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
• Experience in verification and debug of IP/subsystem/SoCs in the Networking domain such as packet processing, bandwidth management, congestion control desired.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with industry-standard simulators, revision control systems, and regression systems.
• Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
• Experience with the full verification life cycle.
• Excellent problem‑solving and communication skills.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

In this role, you will own the full verification life‑cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, building constrained‑random verification environments capable of exposing corner‑case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

Responsibilities

Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.

• Identify and write all types of coverage measures for stimulus and corner‑cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Measure to identify verification holes and to show progress towards tape‑out.
• Create a constrained‑random verification environment using SystemVerilog and Universal Verification Methodology (UVM).

EEO Statement

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.

Benefits

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.