Senior Circuit Silicon Correlation DFT Engineer

NVIDIA Corporation; Bengaluru; Hybrid; INR 4,000,000 - 8,000,000; Full time

Job summary

NVIDIA in Bengaluru is seeking a Senior Circuit Silicon Correlation DFT Engineer to drive advanced DFT and ATPG initiatives in deep submicron processes.

You will lead cross-functional efforts to correlate silicon results with pre-silicon models, develop RAM testing methodologies, and strengthen RTL/gate level verification using VCS and Tessent.

The role requires 8+ years in DFT, strong scripting skills, and a leadership mindset in a hybrid work environment.

Qualifications

• BSEE or MS in Electrical/Electronics Engineering with 8+ years of experience.
• Strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
• Experience bringing up RTL/gate level simulation and debugging testcases.
• RAM circuit understanding and correlation for RAM types.
• Proficiency with VLSI tools like VCS and Tessent.
• Scripting in Python, Perl, Tcl; automation helpful.
• STA experience; post-silicon data gathering a plus.

Responsibilities

• Participate in ground breaking Processor design and debug in deep submicron technologies.
• Work with multifunctional team on silicon characterization and correlation to pre-silicon Performance and Power models.
• Generate ATPG patterns for Silicon speed path debug.
• RTL and gate level verification for ATPG, non-ATPG patterns.
• Correlating diagnosis results to map to real design failures; root cause learnings for pre-silicon sign-off.
• RAM correlation by studying RAM circuit failure mechanisms and improving RAM testing methods.
• Develop new methodologies using DFT infrastructure to analyze mis-correlation in logic and around RAM.

Skills

DFT

ATPG/fault models

RTL/gate level simulation

RAM architecture/ testing

VLSI tools (VCS)

Tessent pattern generation

Scripting: Python/Perl/Tcl

STA basics

Leadership experience

8+ years experience

Education

BSEE

MS in Electrical/Electronics

Tools

VCS

Tessent

Python

Perl

Tcl

Make

Job description

## Senior Circuit Silicon Correlation DFT EngineerApplylocations: India, Bengalurutime type: Full timeposted on: Posted Todayjob requisition id: JR2012806NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.**What will you be doing:*** Participate in ground breaking Processor design and debug in deep submicron technologies.* Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.* Responsible for generating ATPG patterns for Silicon speed path debug.* RTL and gate level verification for ATPG, non-ATPG patterns.* Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.* RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon* Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run* Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.**What we need to see:*** BSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience; Prior leadership experience a certain plus.* Good understanding of Design-for-test(DFT) and logic design is required.* Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.* Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.* Basics of circuits and RAM functionality/architecture will be helpful.* Experience in VLSI simulation tools like VCS etc* Experience with pattern generation using tools such as tessent.* Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.* Prior experience in STA and basic understanding of circuit concepts will help in the role.* Post-Silicon data gathering experience is a plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.#LI-Hybrid