Circuit Silicon Correlation DFT Engineer

NVIDIA Corporation; Bengaluru; Hybrid; INR 1,000,000 - 2,000,000; Full time

Job summary

A leading technology company in Bengaluru is seeking a Circuit Silicon Correlation DFT Engineer to participate in cutting-edge processor design and debug within deep submicron technologies. Successful candidates will have a solid understanding of Design-for-Test methodologies and experience in VLSI simulation tools. This role offers an opportunity to work in a multi-functional team and contribute to innovative solutions in the semiconductor industry.

Qualifications

• 3+ years of experience in electrical or electronics engineering.
• Solid understanding of DFT including scan and ATPG.
• Experience with RTL/gate level simulation and debugging.

Responsibilities

• Participate in Processor design and debug in deep submicron technologies.
• Generate ATPG patterns for silicon speed path debug.
• Correlate diagnosis results to real design failures.

Skills

Design-for-test (DFT)

Logic design

VLSI simulation tools

Scripting languages (Python, Perl, Tcl)

Circuit functionality/architecture

Education

BSEE

MS in Electrical or Electronics Engineering

Tools

VCS

Tessent

Job description

Circuit Silicon Correlation DFT Engineer page is loaded## Circuit Silicon Correlation DFT Engineerlocations: India, Bengalurutime type: Full timeposted on: Posted Todayjob requisition id: JR2012806NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.**What will you be doing:*** Participate in ground breaking Processor design and debug in deep submicron technologies.* Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.* Responsible for generating ATPG patterns for Silicon speed path debug.* RTL and gate level verification for ATPG, non-ATPG patterns.* Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.* RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon* Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run* Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.**What we need to see:*** BSEE required/MS preferred in Electrical or Electronics Engineering with 3+ years experience; Prior leadership experience a certain plus.* Good understanding of Design-for-test(DFT) and logic design is required.* Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.* Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.* Basics of circuits and RAM functionality/architecture will be helpful.* Experience in VLSI simulation tools like VCS etc* Experience with pattern generation using tools such as tessent.* Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.* Prior experience in STA and basic understanding of circuit concepts will help in the role.* Post-Silicon data gathering experience is a plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.#LI-Hybrid